From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 May 2013 23:04:27 +0200 (CEST) Received: from www.linutronix.de ([62.245.132.108]:43083 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S6835069Ab3EBVEXHxir0 (ORCPT ); Thu, 2 May 2013 23:04:23 +0200 Received: from localhost ([127.0.0.1]) by Galois.linutronix.de with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1UY0fs-0007nA-VE; Thu, 02 May 2013 23:04:21 +0200 Date: Thu, 2 May 2013 23:04:19 +0200 (CEST) From: Thomas Gleixner To: David Daney cc: linux-mips@linux-mips.org, ralf@linux-mips.org, Linus Torvalds , linux-kernel@vger.kernel.org, David Daney , Jonas Gorski Subject: Re: [PATCH] MIPS: Enable interrupts before WAIT instruction. In-Reply-To: <1367527692-25809-1-git-send-email-ddaney.cavm@gmail.com> Message-ID: References: <1367527692-25809-1-git-send-email-ddaney.cavm@gmail.com> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 36319 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tglx@linutronix.de Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On Thu, 2 May 2013, David Daney wrote: > From: David Daney > > As noted by Thomas Gleixner: > > commit cdbedc61c8 (mips: Use generic idle loop) broke MIPS as I did > not realize that MIPS wants to invoke the wait instructions with > interrupts enabled. > > Instead of enabling interrupts in arch_cpu_idle() as Thomas' initial > patch does, we follow Linus' suggestion of doing it in the assembly > code to prevent the compiler from rearranging things. Yeah, that looks way more sane. > Signed-off-by: David Daney > Reported-by: EunBong Song > Cc: Thomas Gleixner > Cc: Jonas Gorski > --- > > This is only very lightly tested, we need more testing before > declaring it the definitive fix. > > arch/mips/kernel/genex.S | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S > index ecb347c..57cda9a 100644 > --- a/arch/mips/kernel/genex.S > +++ b/arch/mips/kernel/genex.S > @@ -132,12 +132,13 @@ LEAF(r4k_wait) > .set noreorder > /* start of rollback region */ > LONG_L t0, TI_FLAGS($28) > - nop > andi t0, _TIF_NEED_RESCHED > bnez t0, 1f > nop > - nop > - nop > + /* Enable interrupts so WAIT will complete */ > + mfc0 t0, CP0_STATUS > + ori t0, ST0_IE > + mtc0 t0, CP0_STATUS > .set mips3 > wait > /* end of rollback region (the region size must be power of two) */ > -- > 1.7.11.7 > >