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Date:   Mon, 27 May 2013 13:45:11 +0100 (BST)
From:   "Maciej W. Rozycki" <macro@linux-mips.org>
To:     David Daney <ddaney.cavm@gmail.com>
cc:     Sanjay Lal <sanjayl@kymasys.com>, kvm@vger.kernel.org,
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        Gleb Natapov <gleb@redhat.com>,
        Marcelo Tosatti <mtosatti@redhat.com>
Subject: Re: [PATCH 00/18] KVM/MIPS32: Support for the new Virtualization
 ASE (VZ-ASE)
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On Mon, 20 May 2013, David Daney wrote:

> >   That's rather risky as the implementation of this register (and its
> > presence in the first place) is processor-specific.  Do you maintain a
> > list of PRId values the use of this register is safe with?
> > 
> 
> FWIW:  The MIPS-VZ architecture module requires the presence of CP0 scratch
> registers that can be used for this in the exception handlers without having
> to worry about using these implementation dependent registers.  For the
> trap-and-emulate only version, there really is no choice other than to
> re-purpose some of the existing CP0 registers.

 Sure, I've just been wondering what the implementation does to make sure 
it does not go astray on a random processor out there.

 FWIW, offhand the ErrorEPC register, that's been universally present 
since MIPS III (and I doubt anyone cares of virtualising on earlier 
implementations), seems to me promising as a better choice -- of course 
that register can get clobbered if an error-class exception happens early 
on in exception processing, but in that case we're in a worse trouble than 
just clobbering one of the guest registers anyway and likely cannot 
recover at all regardless.

  Maciej