Linux MIPS Architecture development
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From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: John Crispin <blogic@openwrt.org>,
	Ralf Baechle <ralf@linux-mips.org>,
	Linux-MIPS <linux-mips@linux-mips.org>
Subject: Re: [PATCH] MIPS: add proper set_mode() to cevt-r4k
Date: Mon, 29 Jul 2013 15:53:13 +0100 (BST)	[thread overview]
Message-ID: <alpine.LFD.2.03.1307291549400.9486@linux-mips.org> (raw)
In-Reply-To: <CAGVrzcYXyWB1bwoKyEFrSO7YEJx9Q_v2vOnnPnqVrFVKiigFrA@mail.gmail.com>

On Mon, 29 Jul 2013, Florian Fainelli wrote:

> It is not clear to me whether this secondary cevt is also a r4k-cevt
> device, or if it is something else? If the IRQ is shared, is there any
> way to differentiate the ralink cevt from the r4k cevt, such that both
> could request the same irq with the IRQF_SHARED flag?

 As from rev. 2 of the MIPS architecture processors are required to 
implement a CP0.Cause.TI bit to indicate a CP0.Count/CP0.Compare timer 
interrupt pending -- so it may all bail down to figuring out what MIPS
architecture level this SoC implements.  FWIW.  HTH.

  Maciej

      parent reply	other threads:[~2013-07-29 14:53 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-29  9:55 [PATCH] MIPS: add proper set_mode() to cevt-r4k John Crispin
2013-07-29 10:40 ` Florian Fainelli
2013-07-29 10:52   ` John Crispin
2013-07-29 11:14     ` Florian Fainelli
2013-07-29 11:14       ` John Crispin
2013-07-30 10:01         ` Florian Fainelli
2013-07-31 19:22       ` David Daney
2013-07-31 19:26         ` Florian Fainelli
2013-08-01  6:15           ` John Crispin
2013-08-01 14:13             ` Ralf Baechle
2013-08-01 14:16               ` John Crispin
2013-07-29 14:53   ` Maciej W. Rozycki [this message]

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