Re: [PATCH 08/16] irqchip/mips-gic: clean up if IPI domain registration fails

[Radu Rendec <radu@rendec.net>]

On Tue, 2026-07-14 at 21:24 +0800, Haofeng Li wrote:
> From: Haofeng Li <lihaofeng@kylinos.cn>
> 
> If gic_register_ipi_domain() fails, the primary IRQ domain and the
> mapped register base are left allocated.
> 
> At this point the CPU interrupt handler has not yet been published.
> Remove the primary domain, unmap the register base, and clear both
> global pointers before returning the error.

IMO this patch should be squashed into the previous one in the series
because it fixes a similar problem in the same function of the same
driver, and the change is very much related.

But please see my comments to the previous patch. I think you are
trying to fix a problem that does not exist.

> Fixes: 8190cc572981 ("irqchip/mips-gic: Only register IPI domain when SMP is enabled")
> 
> Signed-off-by: Haofeng Li <lihaofeng@kylinos.cn>
> ---
>  drivers/irqchip/irq-mips-gic.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index 85fe0d8a34c5..2f2ba54f227f 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
> @@ -968,8 +968,13 @@ static int __init gic_of_init(struct device_node *node,
>  	}
>  
>  	ret = gic_register_ipi_domain(node);
> -	if (ret)
> +	if (ret) {
> +		irq_domain_remove(gic_irq_domain);
> +		gic_irq_domain = NULL;
> +		iounmap(mips_gic_base);
> +		mips_gic_base = NULL;
>  		return ret;
> +	}
>  
>  	if (cpu_has_veic) {
>  		/* Always use vector 1 in EIC mode */