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Date:   Mon, 23 Apr 2018 00:31:24 -0400
From:   okaya@codeaurora.org
To:     Huacai Chen <chenhc@lemote.com>
Cc:     Ralf Baechle <ralf@linux-mips.org>,
        James Hogan <james.hogan@mips.com>, linux-mips@linux-mips.org,
        Fuxin Zhang <zhangfx@lemote.com>,
        Zhangjin Wu <wuzhangjin@gmail.com>,
        Huacai Chen <chenhuacai@gmail.com>, stable@vger.kernel.org
Subject: Re: [PATCH] MIPS: io: Add barrier after register read in inX()
In-Reply-To: <1524455600-30384-1-git-send-email-chenhc@lemote.com>
References: <1524455600-30384-1-git-send-email-chenhc@lemote.com>
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On 2018-04-22 23:53, Huacai Chen wrote:
> While a barrier is present in the outX() functions before the register
> write, a similar barrier is missing in the inX() functions after the
> register read. This could allow memory accesses following inX() to
> observe stale data.
> 
> This patch is very similar to commit a1cc7034e33d12dc1 ("MIPS: io: Add
> barrier after register read in readX()"). Because war_io_reorder_wmb()
> is both used by writeX() and outX(), if readX() need a barrier then so
> does inX().
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
>  arch/mips/include/asm/io.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index a7d0b83..cea8ad8 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -414,6 +414,8 @@ static inline type pfx##in##bwlq##p(unsigned long 
> port)			\
>  	__val = *__addr;						\
>  	slow;								\
>  									\
> +	/* prevent prefetching of coherent DMA data prematurely */	\
> +	rmb();								\
>  	return pfx##ioswab##bwlq(__addr, __val);			\
>  }

Typically read barrier is applied after register read.