From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Nov 2009 09:12:18 +0100 (CET) Received: from mail-iw0-f181.google.com ([209.85.223.181]:46632 "EHLO mail-iw0-f181.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492267AbZKQIML (ORCPT ); Tue, 17 Nov 2009 09:12:11 +0100 Received: by iwn11 with SMTP id 11so6477768iwn.22 for ; Tue, 17 Nov 2009 00:12:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:cc:content-type; bh=7UGFyF7iQWdY+I2mgsoWO8tzDL6LoCWj3nSYg56E074=; b=dljevj299f+RvY9ai9OpTvEAvF1lqE8TGNWJaKEjApPxyQDG0nfU8sLHS0+yz2a/P1 rRUY7QsEBQlia0D6SKn54ok56wnKg8GMg0Y5R+WLrHwbtiF3ubNyVgeCC1ITTTE8EAp+ rALs6pLObD1t16+py2YcHmtwPFAEhCWSYYCVg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; b=LyO092cpq5znqniIZ42ff2jWJ51MMFyNMoNkb218oS/KFvBqOjieAIdnTrOOPZaZ9s izrBj5bExKsc+q/CK+b9jLjNlPupINzgkDYSgYVFkFVKYaK6kWKLPtcVOb3NhXkORd+N jt6oIk8ANs/3FRidJv2fTC/5lTPQZZnALtLRE= MIME-Version: 1.0 Received: by 10.231.170.201 with SMTP id e9mr811156ibz.15.1258445523167; Tue, 17 Nov 2009 00:12:03 -0800 (PST) Date: Tue, 17 Nov 2009 16:12:03 +0800 Message-ID: Subject: why it not write those 6bits to entrylo0/1 register? From: figo zhang To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Content-Type: multipart/alternative; boundary=00504501810260acd404788cae31 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24936 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: figo1802@gmail.com Precedence: bulk X-list: linux-mips --00504501810260acd404788cae31 Content-Type: text/plain; charset=ISO-8859-1 hi, all, i have a qusetion , in arch/mips/mm/tlb-r4k.c, __update_tlb() function: 321#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 322 write_c0_entrylo0(ptep->pte_high); 323 ptep++; 324 write_c0_entrylo1(ptep->pte_high); 325#else 326 write_c0_entrylo0(pte_val(*ptep++) >> 6); 327 write_c0_entrylo1(pte_val(*ptep) >> 6); 328#endif why this right shift 6 bits? this 6 bits contain some important bit, such as: C: [bit3~5]: cohereny attribute of page D: V: G: and how the kernel write the this 6 bit to entrylo0/1 register? Best, Figo.zhang --00504501810260acd404788cae31 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
hi, all,
i have a qusetion , in arch/mips/mm/tlb-r4k.c, __update_tlb() function= :
321 #if=A0defined(CONFIG_64BIT_PHYS_A= DDR)=A0&&=A0defined(CONFIG_CPU_MIPS32)
322 =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0write_c0_entrylo0(ptep->pte_high);
323 =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0ptep++;
324 =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0write_c0_entrylo1(ptep->pte_high);
325 #else
326 =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0write_c0_entrylo0(pte_val(*ptep++)=A0>>=A06);
327 =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0write_c0_entrylo1(pte_val(*ptep)=A0>>=A06);
328 #endif
=A0
why this right shift 6 bits? this 6 bits contain some im= portant bit, such as:
C: [bit3~5]: cohereny attribute of page
D:
V:
G:
=A0
and how the kernel write the this 6 bit to entrylo0/1 register?
=A0
Best,
Figo.zhang
--00504501810260acd404788cae31--