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Tue, 8 Jul 2025 17:42:57 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: T0d515a0de5731984 Date: Tue, 08 Jul 2025 22:42:37 +0100 From: "Jiaxun Yang" To: "Gregory CLEMENT" , "Thomas Bogendoerfer" Cc: "Vladimir Kondratiev" , =?UTF-8?Q?Th=C3=A9o_Lebrun?= , "Tawfik Bayouk" , "Thomas Petazzoni" , "linux-mips@vger.kernel.org" , linux-kernel@vger.kernel.org Message-Id: In-Reply-To: <20250708-smp_calib-v3-2-6dabf01a7d9f@bootlin.com> References: <20250708-smp_calib-v3-0-6dabf01a7d9f@bootlin.com> <20250708-smp_calib-v3-2-6dabf01a7d9f@bootlin.com> Subject: Re: [PATCH v3 2/2] MIPS: CPS: Optimise delay CPU calibration for SMP Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82025=E5=B9=B47=E6=9C=888=E6=97=A5=E5=91=A8=E4=BA=8C =E4=B8=8B=E5= =8D=882:46=EF=BC=8CGregory CLEMENT=E5=86=99=E9=81=93=EF=BC=9A > On MIPS architecture with CPS-based SMP support, all CPU cores in the > same cluster run at the same frequency since they share the same L2 > cache, requiring a fixed CPU/L2 cache ratio. > > This allows to implement calibrate_delay_is_known(), which will return > 0 (triggering calibration) only for the primary CPU of each > cluster. For other CPUs, we can simply reuse the value from their > cluster's primary CPU core. > > With the introduction of this patch, a configuration running 32 cores > spread across two clusters sees a significant reduction in boot time > by approximately 600 milliseconds. > > Signed-off-by: Gregory CLEMENT Reviewed-by: Jiaxun Yang > --- > arch/mips/kernel/smp-cps.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c > index=20 > 6c5f15293a8e58a701601b242f43ba19a6814f06..22d4f9ff3ae2671b07da5bb14915= 4c686e07b209=20 > 100644 > --- a/arch/mips/kernel/smp-cps.c > +++ b/arch/mips/kernel/smp-cps.c > @@ -281,6 +281,17 @@ static void __init cps_smp_setup(void) > #endif /* CONFIG_MIPS_MT_FPAFF */ > } >=20 > +unsigned long calibrate_delay_is_known(void) > +{ > + int first_cpu_cluster =3D 0; > + > + /* The calibration has to be done on the primary CPU of the cluster = */ > + if (mips_cps_first_online_in_cluster(&first_cpu_cluster)) > + return 0; > + > + return cpu_data[first_cpu_cluster].udelay_val; > +} > + > static void __init cps_prepare_cpus(unsigned int max_cpus) > { > unsigned int nclusters, ncores, core_vpes, nvpe =3D 0, c, cl, cca; > > --=20 > 2.47.2 --=20 - Jiaxun