* [PATCH 0/3] Added uncached accelerated CPU feature
@ 2009-05-08 6:30 Zhang Le
2009-05-08 6:30 ` [PATCH 1/3] MIPS: added cpu_has_uncached_accelerated feature Zhang Le
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Zhang Le @ 2009-05-08 6:30 UTC (permalink / raw)
To: linux-mips; +Cc: Zhang Le
This patchset adds uncached accelerated CPU feature and handles write_combine
parameter in pci_mmap_page_range function.
Zhang Le (3):
MIPS: added cpu_has_uncached_accelerated feature
MIPS: Loongson 2 has cpu_has_uncached_accelerated feature
MIPS: handle write_combine in pci_mmap_page_range
arch/mips/include/asm/cpu-features.h | 4 ++++
arch/mips/include/asm/cpu.h | 1 +
.../asm/mach-lemote/cpu-feature-overrides.h | 1 +
arch/mips/kernel/cpu-probe.c | 4 ++--
arch/mips/pci/pci.c | 8 ++++++--
5 files changed, 14 insertions(+), 4 deletions(-)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] MIPS: added cpu_has_uncached_accelerated feature
2009-05-08 6:30 [PATCH 0/3] Added uncached accelerated CPU feature Zhang Le
@ 2009-05-08 6:30 ` Zhang Le
2009-05-08 6:30 ` [PATCH 2/3] MIPS: Loongson 2 has " Zhang Le
2009-05-08 6:30 ` [PATCH 3/3] MIPS: handle write_combine in pci_mmap_page_range Zhang Le
2 siblings, 0 replies; 6+ messages in thread
From: Zhang Le @ 2009-05-08 6:30 UTC (permalink / raw)
To: linux-mips; +Cc: Zhang Le
Signed-off-by: Zhang Le <r0bertz@gentoo.org>
---
arch/mips/include/asm/cpu-features.h | 4 ++++
arch/mips/include/asm/cpu.h | 1 +
arch/mips/kernel/cpu-probe.c | 4 ++--
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c0047f8..63a34d3 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -220,6 +220,10 @@
#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
#endif
+#ifndef cpu_has_uncached_accelerated
+#define cpu_has_uncached_accelerated (cpu_data[0].options & MIPS_CPU_UNCACHED_ACCELERATED)
+#endif
+
#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
#endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 3bdc0e3..846477b 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -265,6 +265,7 @@ enum cpu_type_enum {
#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
+#define MIPS_CPU_UNCACHED_ACCELERATED 0x00400000 /* CPU has uncached accelerated feature */
/*
* CPU ASE encodings
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b13b8eb..1910ccf 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -547,7 +547,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
- MIPS_CPU_LLSC;
+ MIPS_CPU_LLSC | MIPS_CPU_UNCACHED_ACCELERATED;
c->tlbsize = 64;
break;
case PRID_IMP_R12000:
@@ -576,7 +576,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
c->isa_level = MIPS_CPU_ISA_III;
c->options = R4K_OPTS |
MIPS_CPU_FPU | MIPS_CPU_LLSC |
- MIPS_CPU_32FPR;
+ MIPS_CPU_32FPR | MIPS_CPU_UNCACHED_ACCELERATED;
c->tlbsize = 64;
break;
}
--
1.6.2.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] MIPS: Loongson 2 has cpu_has_uncached_accelerated feature
2009-05-08 6:30 [PATCH 0/3] Added uncached accelerated CPU feature Zhang Le
2009-05-08 6:30 ` [PATCH 1/3] MIPS: added cpu_has_uncached_accelerated feature Zhang Le
@ 2009-05-08 6:30 ` Zhang Le
2009-05-08 6:30 ` [PATCH 3/3] MIPS: handle write_combine in pci_mmap_page_range Zhang Le
2 siblings, 0 replies; 6+ messages in thread
From: Zhang Le @ 2009-05-08 6:30 UTC (permalink / raw)
To: linux-mips; +Cc: Zhang Le
Signed-off-by: Zhang Le <r0bertz@gentoo.org>
---
.../asm/mach-lemote/cpu-feature-overrides.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h
index 52ec54b..700dd17 100644
--- a/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h
@@ -50,6 +50,7 @@
#define cpu_has_tlb 1
#define cpu_has_tx39_cache 0
#define cpu_has_userlocal 0
+#define cpu_has_uncached_accelerated 1
#define cpu_has_vce 0
#define cpu_has_vtag_icache 0
#define cpu_has_watch 1
--
1.6.2.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] MIPS: handle write_combine in pci_mmap_page_range
2009-05-08 6:30 [PATCH 0/3] Added uncached accelerated CPU feature Zhang Le
2009-05-08 6:30 ` [PATCH 1/3] MIPS: added cpu_has_uncached_accelerated feature Zhang Le
2009-05-08 6:30 ` [PATCH 2/3] MIPS: Loongson 2 has " Zhang Le
@ 2009-05-08 6:30 ` Zhang Le
2009-05-08 8:54 ` yanh
2 siblings, 1 reply; 6+ messages in thread
From: Zhang Le @ 2009-05-08 6:30 UTC (permalink / raw)
To: linux-mips; +Cc: Zhang Le
Signed-off-by: Zhang Le <r0bertz@gentoo.org>
---
arch/mips/pci/pci.c | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index b0eb9e7..4ca53ef 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -346,10 +346,14 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
return -EINVAL;
/*
- * Ignore write-combine; for now only return uncached mappings.
+ * For write-combine, return uncached accelerated mappings if CPU
+ * supports; otherwise, return uncached mappings.
*/
prot = pgprot_val(vma->vm_page_prot);
- prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
+ if (write_combine && cpu_has_uncached_accelerated)
+ prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED_ACCELERATED;
+ else
+ prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
vma->vm_page_prot = __pgprot(prot);
return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
--
1.6.2.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] MIPS: handle write_combine in pci_mmap_page_range
2009-05-08 6:30 ` [PATCH 3/3] MIPS: handle write_combine in pci_mmap_page_range Zhang Le
@ 2009-05-08 8:54 ` yanh
2009-05-08 10:18 ` Zhang Le
0 siblings, 1 reply; 6+ messages in thread
From: yanh @ 2009-05-08 8:54 UTC (permalink / raw)
To: Zhang Le; +Cc: linux-mips
在 2009-05-08五的 14:30 +0800,Zhang Le写道:
> Signed-off-by: Zhang Le <r0bertz@gentoo.org>
> ---
> arch/mips/pci/pci.c | 8 ++++++--
> 1 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
> index b0eb9e7..4ca53ef 100644
> --- a/arch/mips/pci/pci.c
> +++ b/arch/mips/pci/pci.c
> @@ -346,10 +346,14 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
> return -EINVAL;
>
> /*
> - * Ignore write-combine; for now only return uncached mappings.
> + * For write-combine, return uncached accelerated mappings if CPU
> + * supports; otherwise, return uncached mappings.
> */
> prot = pgprot_val(vma->vm_page_prot);
> - prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
> + if (write_combine && cpu_has_uncached_accelerated)
> + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED_ACCELERATED;
> + else
> + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
> vma->vm_page_prot = __pgprot(prot);
This should be definietely wrong for MMIOs.
uncache accelleration should only be enabled for addresses which have no
side effect when doing write combine such as video memory.
>
> return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] MIPS: handle write_combine in pci_mmap_page_range
2009-05-08 8:54 ` yanh
@ 2009-05-08 10:18 ` Zhang Le
0 siblings, 0 replies; 6+ messages in thread
From: Zhang Le @ 2009-05-08 10:18 UTC (permalink / raw)
To: yanh; +Cc: linux-mips
[-- Attachment #1: Type: text/plain, Size: 2338 bytes --]
On 16:54 Fri 08 May , yanh wrote:
>
> 在 2009-05-08五的 14:30 +0800,Zhang Le写道:
> > Signed-off-by: Zhang Le <r0bertz@gentoo.org>
> > ---
> > arch/mips/pci/pci.c | 8 ++++++--
> > 1 files changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
> > index b0eb9e7..4ca53ef 100644
> > --- a/arch/mips/pci/pci.c
> > +++ b/arch/mips/pci/pci.c
> > @@ -346,10 +346,14 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
> > return -EINVAL;
> >
> > /*
> > - * Ignore write-combine; for now only return uncached mappings.
> > + * For write-combine, return uncached accelerated mappings if CPU
> > + * supports; otherwise, return uncached mappings.
> > */
> > prot = pgprot_val(vma->vm_page_prot);
> > - prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
> > + if (write_combine && cpu_has_uncached_accelerated)
> > + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED_ACCELERATED;
> > + else
> > + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
> > vma->vm_page_prot = __pgprot(prot);
> This should be definietely wrong for MMIOs.
> uncache accelleration should only be enabled for addresses which have no
> side effect when doing write combine such as video memory.
Actually, currently write_combine is true only for prefetchable pci memory:
http://lxr.linux.no/linux+v2.6.29/drivers/pci/pci-sysfs.c#L711
And currently on fuloong 2f box, there is only one prefetchable pci memory
region, which just belongs to video card:
zhangle@2f /sys/devices/pci0000:00 (n32) $ find -name "*wc" -exec ls -l {} \;
-rw------- 1 root root 256M 2009-05-08 03:25 ./0000:00:08.0/resource0_wc
So, are we talking about the same thing?
Also, I have observed that this region is larger than the actual video ram size
32M. However, libpciaccess only mapped 32M into X's address space:
zhangle@2f ~ (n32) $ sudo cat /proc/$(pidof X)/maps | grep wc$
2b354000-2d354000 rw-s 50000000 00:00 1882 /sys/devices/pci0000:00/0000:00:08.0/resource0_wc
So, I guess this should be just ok, right?
Any other risks?
> >
> > return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
>
--
Zhang, Le
Gentoo/Loongson Developer
http://zhangle.is-a-geek.org
0260 C902 B8F8 6506 6586 2B90 BC51 C808 1E4E 2973
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2009-05-08 10:19 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2009-05-08 6:30 [PATCH 0/3] Added uncached accelerated CPU feature Zhang Le
2009-05-08 6:30 ` [PATCH 1/3] MIPS: added cpu_has_uncached_accelerated feature Zhang Le
2009-05-08 6:30 ` [PATCH 2/3] MIPS: Loongson 2 has " Zhang Le
2009-05-08 6:30 ` [PATCH 3/3] MIPS: handle write_combine in pci_mmap_page_range Zhang Le
2009-05-08 8:54 ` yanh
2009-05-08 10:18 ` Zhang Le
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