From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: "Théo Lebrun" <theo.lebrun@bootlin.com>,
"Andrew Lunn" <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Paolo Abeni" <pabeni@redhat.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Nicolas Ferre" <nicolas.ferre@microchip.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Richard Cochran" <richardcochran@gmail.com>,
"Russell King" <linux@armlinux.org.uk>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>,
"Gregory CLEMENT" <gregory.clement@bootlin.com>
Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-mips@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Tawfik Bayouk <tawfik.bayouk@mobileye.com>
Subject: Re: [PATCH net-next 10/13] net: macb: Add "mobileye,eyeq5-gem" compatible
Date: Thu, 27 Mar 2025 10:13:39 +0200 [thread overview]
Message-ID: <d47e7da3-4b84-4688-a1f1-8019383a3e48@tuxon.dev> (raw)
In-Reply-To: <D8PITUNTWTXA.366TNSXDUL48G@bootlin.com>
Hi, Theo,
On 25.03.2025 19:25, Théo Lebrun wrote:
>>> + }
>>> +
>>> + regmap_read(regmap, gp, ®);
>>> + reg &= ~EYEQ5_OLB_GP_RGMII_DRV;
>>> + if (phy_interface_mode_is_rgmii(bp->phy_interface))
>>> + reg |= FIELD_PREP(EYEQ5_OLB_GP_RGMII_DRV, 0x9);
>>> + reg |= EYEQ5_OLB_GP_TX_SWRST_DIS | EYEQ5_OLB_GP_TX_M_CLKE;
>>> + reg |= EYEQ5_OLB_GP_SYS_SWRST_DIS | EYEQ5_OLB_GP_SYS_M_CLKE;
>>> + regmap_write(regmap, gp, reg);
>> To me it looks like this code could be abstracted as a phy driver. E.g.,
>> check the init_reset_optional() and its usage on "cdns,zynqmp-gem" (phy
>> driver here: drivers/phy/xilinx/phy-zynqmp.c).
> I thought about that question. Options to implement that sequence are:
>
> - (1) Implement a separate PHY driver, what you are proposing. I just
> made a prototype branch to see what it'd look like. Nothing too
> surprising; mostly the above sequence is copy-pasted inside
> phy_init|power_on(). I see two issues:
>
> - First, a practical one. This adds a lot of boilerplate for no
> obvious benefit compared to a raw registers read/write sequence
> inside macb_config->init().
The macb is used by various platforms. If the settings proposed in this
patch (platform specific AFAICT) could be abstracted and used with generic
APIs I think would be better this way.
>
> The main reason for that boilerplate is to allow reuse of a PHY
> across MACs;
And/or avoid having platform specific code in the macb driver.
> here we already know that cannot be useful because
> the EyeQ5 has two GEMs and nothing else. Those registers are
> EyeQ5-specific.
>
> - Second, a semantic one. The registers we are touching are *not*
> the PHY's registers. They are configuring the PHY's integration:
> its input PLL, resets, etc.
>
> - (2) Second, taking into account that what we are configuring isn't
> the PHY itself but its resources, we could try modeling each
> individual register+field as a reset / clock / pin control (there is
> some drive strength in here, *I think*). Issue: this would get
> messy, fast.
> - A single register would expose many resources.
> - The sequence in macb_config->init() would need to be the exact
> same order. IE we can't abstract much.
>
> Something like this pseudocode (which is a bad idea, we'd all agree
> here):
>
> reset_deassert(bp->eq5_sgmii_reset);
> reset_deassert(bp->eq5_sgmii_reset_pwr);
> reset_deassert(bp->eq5_phy_reset_tx);
> reset_deassert(bp->eq5_phy_reset_sys);
>
> if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
> pinctrl_select_state(bp->eq5_phy_input_pinctrl, bp->eq5_pins_sgmii);
>
> reset_deassert(bp->eq5_sgmii_reset);
> clk_prepare_enable(bp->eq5_sgmii_phy_input_pll);
>
> reset_deassert(bp->eq5_sgmii_reset_pwr);
> } else {
> pinctrl_select_state(bp->eq5_pinctrl, bp->eq5_pins_rgmii);
> }
>
> reset_deassert(bp->eq5_phy_reset_tx);
> reset_deassert(bp->eq5_phy_reset_sys);
> clk_prepare_enable(bp->eq5_phy_mclk_tx);
> clk_prepare_enable(bp->eq5_phy_mclk_sys);
This looks complicated to me.
>
> - (3) Keep the sequence in macb_config->init(). Plain and simple.
> - Issue: it is somewhat unrelated platform-specific code that's
> present inside macb_main.c.
For maintainability I would prefer to avoid this.
>
> The two serious options are (1) and (3).
> (1) is what you proposed and (3) is what's in the series.
I prefer (1) if it can be done.
Thank you,
Claudiu
next prev parent reply other threads:[~2025-03-27 8:13 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-21 19:09 [PATCH net-next 00/13] Support the Cadence MACB/GEM instances on Mobileye EyeQ5 SoCs Théo Lebrun
2025-03-21 19:09 ` [PATCH net-next 01/13] dt-bindings: net: cdns,macb: add Mobileye EyeQ5 ethernet interface Théo Lebrun
2025-03-21 20:37 ` Rob Herring (Arm)
2025-03-21 20:49 ` Andrew Lunn
2025-03-24 16:14 ` Théo Lebrun
2025-03-21 19:09 ` [PATCH net-next 02/13] dt-bindings: net: cdns,macb: allow tsu_clk without tx_clk Théo Lebrun
2025-03-24 16:30 ` Rob Herring
2025-03-27 14:55 ` Théo Lebrun
2025-03-21 19:09 ` [PATCH net-next 03/13] dt-bindings: net: cdns,macb: allow dma-coherent Théo Lebrun
2025-03-24 16:31 ` Rob Herring (Arm)
2025-03-21 19:09 ` [PATCH net-next 04/13] net: macb: use BIT() macro for capability definitions Théo Lebrun
2025-03-21 20:50 ` Andrew Lunn
2025-03-21 19:09 ` [PATCH net-next 05/13] net: macb: add no LSO capability (MACB_CAPS_NO_LSO) Théo Lebrun
2025-03-21 20:51 ` Andrew Lunn
2025-03-24 8:18 ` Claudiu Beznea
2025-03-26 10:04 ` Théo Lebrun
2025-03-21 19:09 ` [PATCH net-next 06/13] net: macb: simplify macb_probe() code touching match data Théo Lebrun
2025-03-21 20:57 ` Andrew Lunn
2025-03-21 19:09 ` [PATCH net-next 07/13] net: macb: move HW IP alignment value to macb_config Théo Lebrun
2025-03-21 21:06 ` Andrew Lunn
2025-03-24 17:49 ` Théo Lebrun
2025-03-24 18:36 ` Andrew Lunn
2025-03-26 5:01 ` Katakam, Harini
2025-03-27 17:07 ` Théo Lebrun
2025-03-21 19:09 ` [PATCH net-next 08/13] net: macb: introduce DMA descriptor helpers (is 64bit? is PTP?) Théo Lebrun
2025-03-24 8:20 ` Claudiu Beznea
2025-03-24 8:55 ` Maxime Chevallier
2025-03-26 10:59 ` Théo Lebrun
2025-03-21 19:09 ` [PATCH net-next 09/13] net: macb: sort #includes Théo Lebrun
2025-03-21 21:11 ` Andrew Lunn
2025-03-21 19:09 ` [PATCH net-next 10/13] net: macb: Add "mobileye,eyeq5-gem" compatible Théo Lebrun
2025-03-24 8:18 ` Claudiu Beznea
2025-03-25 17:25 ` Théo Lebrun
2025-03-27 8:13 ` Claudiu Beznea [this message]
2025-03-21 19:09 ` [PATCH net-next 11/13] MIPS: mobileye: add EyeQ5 DMA IOCU support Théo Lebrun
2025-03-21 19:09 ` [PATCH net-next 12/13] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers Théo Lebrun
2025-03-21 19:09 ` [PATCH net-next 13/13] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs Théo Lebrun
2025-03-21 21:16 ` Andrew Lunn
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