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Subject: Re: [PATCH 4/4] MIPS: emulate CPUCFG instruction on older Loongson64
 cores
To:     Huacai Chen <chenhc@lemote.com>, WANG Xuerui <git@xen0n.name>
Cc:     "open list:MIPS" <linux-mips@vger.kernel.org>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>,
        Tiezhu Yang <yangtiezhu@loongson.cn>
References: <20200502133846.40590-1-git@xen0n.name>
 <20200502133846.40590-5-git@xen0n.name>
 <CAAhV-H5U+KHzORKVjrteYggF24WUAz+dsNL_-YJ_0vKvo2Mw1A@mail.gmail.com>
From:   Wang Xuerui <i@xen0n.name>
Message-ID: <da2aa0e8-ee8c-18a1-ee04-b57678ed1bfc@xen0n.name>
Date:   Sun, 3 May 2020 15:58:45 +0800
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On 5/3/20 2:31 PM, Huacai Chen wrote:

> Hi, Xuerui,
>
> On Sat, May 2, 2020 at 9:47 PM WANG Xuerui <git@xen0n.name> wrote:
>> +
>> +static int simulate_loongson3_csr_cpucfg(struct pt_regs *regs,
>> +                                       unsigned int opcode)
> Maybe simulate_loongson3_cpucfg() is a better name?

Fair point, I was thinking CPUCFG is a part of bigger CSR instructions, 
so kept the prefix; I don't know what other CSR instructions are 
accessible from user-space anyway. (Loongson, could you guys *please* 
release the ISA docs btw?)

Anyway, by removing the "csr" part it feels more consistent with other 
parts of the patch. I'll send v2 soon.