Re: [PATCH 01/10] MIPS: smp: Make IPI interrupts scalable

["Jiaxun Yang" <jiaxun.yang@flygoat.com>]

在2024年7月4日七月 上午5:26，Maciej W. Rozycki写道：
> On Thu, 4 Jul 2024, Jiaxun Yang wrote:
>
>> It has been tested on MIPS Boston I6500, malta SOC-It, Loongson-2K,
>
>  SOC-it (or SOC-it 101 to be precise) is the name of a bus controller:
>
> System controller/revision =    MIPS SOC-it 101 OCP / 1.3   SDR-FW-4:1
>
> used across numerous platforms from the M4K core onwards, UP, MT, or MP.  
> I think it would make sense if you revealed the processor type instead.

Sure, sorry to be vague on the platform detail.

I actually tried on two Malta configurations, CoreFPGA6 interAptiv 2MPF (2 cores, 2 VPE, 4TC),
and CoreFPGA3 34Kc MT (2VPE 9TC).

>
>> I don't really know broadcom platforms and SGI platforms well so
>> changes to those platforms are kept minimal (no functional change).
>
>  Technically I could run it on my SB1250, but I'm too overloaded now to 
> commit to any timescale.  Sorry.

No worries, I'll try to fetch a BMIPS3000 SMP router to get Broadcom platform
undercover.

Thanks
>
>   Maciej

-- 
- Jiaxun