From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15052C433EF for ; Sat, 9 Jul 2022 16:49:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229490AbiGIQtq (ORCPT ); Sat, 9 Jul 2022 12:49:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229447AbiGIQtq (ORCPT ); Sat, 9 Jul 2022 12:49:46 -0400 X-Greylist: delayed 2278 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Sat, 09 Jul 2022 09:49:44 PDT Received: from wp175.webpack.hosteurope.de (wp175.webpack.hosteurope.de [IPv6:2a01:488:42:1000:50ed:84b6::]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B394027162; Sat, 9 Jul 2022 09:49:44 -0700 (PDT) Received: from p54bc6cd6.dip0.t-ipconnect.de ([84.188.108.214] helo=[192.168.1.113]); authenticated by wp175.webpack.hosteurope.de running ExIM with esmtpsa (TLS1.3:ECDHE_RSA_AES_128_GCM_SHA256:128) id 1oAD3W-0007uY-BP; Sat, 09 Jul 2022 18:11:42 +0200 Message-ID: Date: Sat, 9 Jul 2022 18:11:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second VPE Content-Language: en-US To: Sander Vanheule , Thomas Bogendoerfer , Martin Blumenstingl Cc: Marc Zyngier , Aleksander Jan Bajkowski , Hauke Mehrtens , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220702190705.5319-1-olek2@wp.pl> <3c9a032edd0fb9b9608ad3ca08d6e3cc38f21464.camel@svanheule.net> <87fsjen2kl.wl-maz@kernel.org> <20220706081901.GA10797@alpha.franken.de> <20220707100630.GC9894@alpha.franken.de> <20220707143930.GA14693@alpha.franken.de> <468a2c8578d099eef0e0106fe273f73f5d70ef94.camel@svanheule.net> From: Birger Koblitz In-Reply-To: <468a2c8578d099eef0e0106fe273f73f5d70ef94.camel@svanheule.net> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-bounce-key: webpack.hosteurope.de;git@birger-koblitz.de;1657385384;a94bfab7; X-HE-SMSGID: 1oAD3W-0007uY-BP Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Hi, On 7/7/22 17:12, Sander Vanheule wrote: > On Thu, 2022-07-07 at 16:39 +0200, Thomas Bogendoerfer wrote: >> On Thu, Jul 07, 2022 at 02:57:15PM +0200, Martin Blumenstingl wrote: >> IMHO there is the problem, irq-mips-cpu.c can only do CPU irq operations >> on the same CPU. I've checked MIPS MT specs and it's possible do >> modify CP0 registers between VPEs. Using that needs changes in >> irq-mips-cpu.c. But mabye that's not woth the effort as probably >> all SMP cabable platforms have some multi processort capable >> interrupt controller implemented. Not sure I can be of much help. That the patch works on the RTL SoCs is mostly empirical and was found in the vendor code. My understanding from the MIPS documentation is that it is not specified what happens when a multi VPE capable IRQ controller triggers CPU interrupts: if multiple VPEs are possible targets, then it is not defined whether one of them gets them (and which one), multiple, or all. So trying to control what happens between VPEs is probably SoC-dependent functionality. Cheers, Birger