From: Marc Zyngier <maz@kernel.org>
To: Huacai Chen <chenhc@lemote.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
"open list:MIPS" <linux-mips@vger.kernel.org>,
Fuxin Zhang <zhangfx@lemote.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
stable <stable@vger.kernel.org>
Subject: Re: [PATCH 1/3] MIPS: Loongson64: Increase NR_IRQS to 320
Date: Fri, 11 Sep 2020 08:44:47 +0100 [thread overview]
Message-ID: <efab39a121918316564168c07cf88539@kernel.org> (raw)
In-Reply-To: <CAAhV-H401y6_9++CStCH=RrfoRw6-hZBWquEAGtGecbTGbVO1Q@mail.gmail.com>
On 2020-09-11 04:24, Huacai Chen wrote:
> Hi, Marc,
>
> On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier <maz@kernel.org> wrote:
>>
>> On 2020-09-09 05:09, Huacai Chen wrote:
>> > Modernized Loongson64 uses a hierarchical organization for interrupt
>> > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ
>> > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
>> > is not enough to represent all interrupts, so let's increase NR_IRQS to
>> > 320.
>> >
>> > Cc: stable@vger.kernel.org
>> > Signed-off-by: Huacai Chen <chenhc@lemote.com>
>> > ---
>> > arch/mips/include/asm/mach-loongson64/irq.h | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h
>> > b/arch/mips/include/asm/mach-loongson64/irq.h
>> > index f5e362f7..0da3017 100644
>> > --- a/arch/mips/include/asm/mach-loongson64/irq.h
>> > +++ b/arch/mips/include/asm/mach-loongson64/irq.h
>> > @@ -7,7 +7,7 @@
>> > /* cpu core interrupt numbers */
>> > #define NR_IRQS_LEGACY 16
>> > #define NR_MIPS_CPU_IRQS 8
>> > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
>> > +#define NR_IRQS 320
>> >
>> > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
>>
>> Why are you hardcoding a random value instead of bumping the constant
>> in NR_IRQS?
> Because INTCs can organized in many kinds of hierarchy, we cannot use
> constants to define a accurate value, but 320 is big enough.
You're not answering my question. You have a parameterized NR_IRQS, and
you're turning it into an absolute constant. Why? I.e:
#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296)
And why 320? Why not 512? or 2^15?
As for a "modernized" setup, the fact that you are not using SPARSE_IRQ
is pretty backward.
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2020-09-11 7:44 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-09 4:09 [PATCH 1/3] MIPS: Loongson64: Increase NR_IRQS to 320 Huacai Chen
2020-09-09 4:09 ` [PATCH 2/3] irqchip/loongson-htvec: Fix initial interrupts clearing Huacai Chen
2020-09-09 4:09 ` [PATCH 3/3] irqchip/loongson-pch-pic: Reserve legacy LPC irqs Huacai Chen
2020-09-10 0:51 ` Jiaxun Yang
2020-09-10 1:40 ` Huacai Chen
2020-09-10 10:08 ` Marc Zyngier
2020-09-11 4:13 ` Huacai Chen
2020-09-11 7:50 ` Marc Zyngier
2020-09-11 10:12 ` Huacai Chen
2020-09-10 16:34 ` Sasha Levin
2020-09-11 0:12 ` Huacai Chen
2020-09-10 10:10 ` [PATCH 1/3] MIPS: Loongson64: Increase NR_IRQS to 320 Marc Zyngier
2020-09-11 3:24 ` Huacai Chen
2020-09-11 7:44 ` Marc Zyngier [this message]
2020-09-11 8:43 ` Huacai Chen
2020-09-11 9:03 ` Marc Zyngier
2020-09-11 9:14 ` Huacai Chen
2020-09-11 9:23 ` Marc Zyngier
2020-09-11 9:40 ` Huacai Chen
2020-09-10 16:34 ` Sasha Levin
2020-09-11 0:11 ` Huacai Chen
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