From: WANG Xuerui <kernel@xen0n.name>
To: linux-mips@vger.kernel.org
Subject: Re: [PATCH v2 0/4] CPUCFG emulation on older Loongson64 cores
Date: Sat, 16 May 2020 19:29:39 +0800 [thread overview]
Message-ID: <f334c7f1-9165-b4d6-deda-6bb3f9c0e8ff@xen0n.name> (raw)
In-Reply-To: <20200503103304.40678-1-git@xen0n.name>
On 5/3/20 6:33 PM, WANG Xuerui wrote:
> This patch series brings the CPUCFG instruction to older Loongson64
> cores, enabling a unified way to query processor characteristics on
> Loongson64 systems. A detailed explanation may be found in the last
> commit.
>
> One unresolved point is how to best introduce machtype-specific bits
> into the generic MIPS code, namely the cpu probing and trap handler
> parts. I have been struggling over whether to lift this logic into
> arch/mips/kernel, but the instruction's encoding (reusing LWC2 opcode)
> might be too invasive to be useful to other MIPS platforms. What do
> people think is the best way forward?
>
> v2:
>
> - Fixed one more typo in loongson_regs.h
> - Merged simulate_loongson3_csr and simulate_loongson3_csr_cpucfg into
> one (simulate_loongson3_cpucfg), per Huacai's suggestion
>
> WANG Xuerui (4):
> MIPS: Loongson64: fix typos in loongson_regs.h
> MIPS: Loongson64: define offsets and known revisions for some CPUCFG
> features
> MIPS: define more Loongson CP0.Config6 and CP0.Diag feature bits
> MIPS: emulate CPUCFG instruction on older Loongson64 cores
>
> arch/mips/Kconfig | 11 ++
> arch/mips/include/asm/cpu-info.h | 9 ++
> .../include/asm/mach-loongson64/cpucfg-emul.h | 67 +++++++++
> .../asm/mach-loongson64/loongson_regs.h | 29 +++-
> arch/mips/include/asm/mipsregs.h | 6 +
> arch/mips/kernel/cpu-probe.c | 129 ++++++++++++++++++
> arch/mips/kernel/traps.c | 45 ++++++
> arch/mips/loongson64/Makefile | 1 +
> arch/mips/loongson64/cpucfg-emul.c | 80 +++++++++++
> 9 files changed, 372 insertions(+), 5 deletions(-)
> create mode 100644 arch/mips/include/asm/mach-loongson64/cpucfg-emul.h
> create mode 100644 arch/mips/loongson64/cpucfg-emul.c
>
Just a friendly ping.
What is the status of this series? I know that I borked the threading of
replies, I can resend if it's the only thing holding the series.
And I think the patch may well need to be reorganized, but no replies
yet. I'm not a professional kernel developer, and any review is appreciated!
next prev parent reply other threads:[~2020-05-16 11:29 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-02 13:38 [PATCH 0/4] CPUCFG emulation on older Loongson64 cores WANG Xuerui
2020-05-02 13:38 ` [PATCH 1/4] MIPS: Loongson64: fix typos in loongson_regs.h WANG Xuerui
2020-05-02 13:38 ` [PATCH 2/4] MIPS: Loongson64: define offsets and known revisions for some CPUCFG features WANG Xuerui
2020-05-02 13:38 ` [PATCH 3/4] MIPS: define more Loongson CP0.Config6 and CP0.Diag feature bits WANG Xuerui
2020-05-02 13:38 ` [PATCH 4/4] MIPS: emulate CPUCFG instruction on older Loongson64 cores WANG Xuerui
2020-05-02 13:59 ` Jiaxun Yang
2020-05-03 6:31 ` Huacai Chen
2020-05-03 7:58 ` Wang Xuerui
2020-05-03 8:25 ` Jiaxun Yang
2020-05-03 10:33 ` [PATCH v2 0/4] CPUCFG emulation " WANG Xuerui
2020-05-16 11:29 ` WANG Xuerui [this message]
2020-05-17 8:38 ` Thomas Bogendoerfer
2020-05-03 10:33 ` [PATCH v2 1/4] MIPS: Loongson64: fix typos in loongson_regs.h WANG Xuerui
2020-05-03 10:33 ` [PATCH v2 2/4] MIPS: Loongson64: define offsets and known revisions for some CPUCFG features WANG Xuerui
2020-05-03 10:33 ` [PATCH v2 3/4] MIPS: define more Loongson CP0.Config6 and CP0.Diag feature bits WANG Xuerui
2020-05-03 10:33 ` [PATCH v2 4/4] MIPS: emulate CPUCFG instruction on older Loongson64 cores WANG Xuerui
2020-05-03 10:50 ` [PATCH v2 RESEND " WANG Xuerui
2020-05-03 15:50 ` Jiaxun Yang
2020-05-04 5:25 ` WANG Xuerui
2020-05-04 6:58 ` Jiaxun Yang
2020-05-17 8:37 ` Thomas Bogendoerfer
2020-05-17 11:39 ` WANG Xuerui
2020-05-17 15:17 ` Thomas Bogendoerfer
2020-05-18 2:44 ` WANG Xuerui
2020-05-19 14:33 ` WANG Xuerui
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