From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Jan 2011 02:58:42 +0100 (CET) Received: from [69.28.251.93] ([69.28.251.93]:54538 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1492841Ab1ANB42 (ORCPT ); Fri, 14 Jan 2011 02:56:28 +0100 Received: (qmail 12274 invoked from network); 14 Jan 2011 01:56:25 -0000 Received: from unknown (HELO vps-1001064-677.cp.jvds.com) (127.0.0.1) by 127.0.0.1 with (DHE-RSA-AES128-SHA encrypted) SMTP; 14 Jan 2011 01:56:25 -0000 Received: by vps-1001064-677.cp.jvds.com (sSMTP sendmail emulation); Thu, 13 Jan 2011 17:56:25 -0800 From: Kevin Cernekee To: Ralf Baechle Cc: , Subject: [PATCH RESEND 5/6] MIPS: Install handlers for BMIPS software IRQs Date: Thu, 13 Jan 2011 17:52:16 -0800 Message-Id: In-Reply-To: <491015d51e5d3d36c517da09e038ecaf@localhost> References: <491015d51e5d3d36c517da09e038ecaf@localhost> User-Agent: vim 7.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 28914 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cernekee@gmail.com Precedence: bulk X-list: linux-mips BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread signaling. Signed-off-by: Kevin Cernekee --- arch/mips/kernel/irq_cpu.c | 14 ++++++-------- 1 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 0262abe..70d4736 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -107,14 +107,12 @@ void __init mips_cpu_irq_init(void) clear_c0_status(ST0_IM); clear_c0_cause(CAUSEF_IP); - /* - * Only MT is using the software interrupts currently, so we just - * leave them uninitialized for other processors. - */ - if (cpu_has_mipsmt) - for (i = irq_base; i < irq_base + 2; i++) - set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller, - handle_percpu_irq); + /* Software interrupts are used for MT/CMT IPI */ + for (i = irq_base; i < irq_base + 2; i++) + set_irq_chip_and_handler(i, cpu_has_mipsmt ? + &mips_mt_cpu_irq_controller : + &mips_cpu_irq_controller, + handle_percpu_irq); for (i = irq_base + 2; i < irq_base + 8; i++) set_irq_chip_and_handler(i, &mips_cpu_irq_controller, -- 1.7.0.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [69.28.251.93] ([69.28.251.93]:54538 "EHLO b32.net" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1492841Ab1ANB42 (ORCPT ); Fri, 14 Jan 2011 02:56:28 +0100 From: Kevin Cernekee Subject: [PATCH RESEND 5/6] MIPS: Install handlers for BMIPS software IRQs Date: Thu, 13 Jan 2011 17:52:16 -0800 Message-ID: In-Reply-To: <491015d51e5d3d36c517da09e038ecaf@localhost> References: <491015d51e5d3d36c517da09e038ecaf@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Message-ID: <20110114015216.zfP3bSiv_WQ1wZf28_TQtBWUry9gZKg-sYgMsS2cyHA@z> BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread signaling. Signed-off-by: Kevin Cernekee --- arch/mips/kernel/irq_cpu.c | 14 ++++++-------- 1 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 0262abe..70d4736 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -107,14 +107,12 @@ void __init mips_cpu_irq_init(void) clear_c0_status(ST0_IM); clear_c0_cause(CAUSEF_IP); - /* - * Only MT is using the software interrupts currently, so we just - * leave them uninitialized for other processors. - */ - if (cpu_has_mipsmt) - for (i = irq_base; i < irq_base + 2; i++) - set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller, - handle_percpu_irq); + /* Software interrupts are used for MT/CMT IPI */ + for (i = irq_base; i < irq_base + 2; i++) + set_irq_chip_and_handler(i, cpu_has_mipsmt ? + &mips_mt_cpu_irq_controller : + &mips_cpu_irq_controller, + handle_percpu_irq); for (i = irq_base + 2; i < irq_base + 8; i++) set_irq_chip_and_handler(i, &mips_cpu_irq_controller, -- 1.7.0.4