From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org
Cc: linuxppc-dev@lists.ozlabs.org, linux-mm@kvack.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [RFC PATCH -V2 09/21] powerpc: Update tlbie/tlbiel as per ISA doc
Date: Thu, 21 Feb 2013 22:17:16 +0530 [thread overview]
Message-ID: <1361465248-10867-10-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1361465248-10867-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This make sure we handle Multiple page size segment correctly.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/hash_native_64.c | 52 +++++++++++++++++++++++++++++---------
1 file changed, 40 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 3d30b23..3bc57e2 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -39,7 +39,7 @@
DEFINE_RAW_SPINLOCK(native_tlbie_lock);
-static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
+static inline void __tlbie(unsigned long vpn, int bpsize, int apsize, int ssize)
{
unsigned long va;
unsigned int penc;
@@ -59,19 +59,33 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
*/
va &= ~(0xffffULL << 48);
- switch (psize) {
+ switch (bpsize) {
case MMU_PAGE_4K:
+ /* clear out bits after (52) [0....52.....63] */
+ va &= ~((1ul << (64 - 52)) - 1);
va |= ssize << 8;
+ va |= mmu_psize_defs[apsize].sllp << 6;
asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
: "memory");
break;
default:
/* We need 14 to 14 + i bits of va */
- penc = mmu_psize_defs[psize].penc[apsize];
- va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
+ penc = mmu_psize_defs[bpsize].penc[apsize];
+ /* clear out bits after (44) [0....44.....63] */
+ va &= ~((1ul << (64 - 44)) - 1);
va |= penc << 12;
va |= ssize << 8;
+ /* Add AVAL part */
+ if (bpsize != apsize) {
+ /*
+ * MPSS, 64K base page size and 16MB parge page size
+ * We don't need all the bits, but this seems to work.
+ * vpn cover upto 65 bits of va. (0...65) and we need
+ * 56..62 bits of va.
+ */
+ va |= ((vpn >> 2) & 0xfe);
+ }
va |= 1; /* L */
asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
@@ -80,7 +94,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
}
}
-static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
+static inline void __tlbiel(unsigned long vpn, int bpsize, int apsize, int ssize)
{
unsigned long va;
unsigned int penc;
@@ -94,18 +108,32 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
*/
va &= ~(0xffffULL << 48);
- switch (psize) {
+ switch (bpsize) {
case MMU_PAGE_4K:
+ /* clear out bits after(52) [0....52.....63] */
+ va &= ~((1ul << (64 - 52)) - 1);
va |= ssize << 8;
+ va |= mmu_psize_defs[apsize].sllp << 6;
asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
: : "r"(va) : "memory");
break;
default:
/* We need 14 to 14 + i bits of va */
- penc = mmu_psize_defs[psize].penc[apsize];
- va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
+ penc = mmu_psize_defs[bpsize].penc[apsize];
+ /* clear out bits after(44) [0....44.....63] */
+ va &= ~((1ul << (64 - 44)) - 1);
va |= penc << 12;
va |= ssize << 8;
+ /* Add AVAL part */
+ if (bpsize != apsize) {
+ /*
+ * MPSS, 64K base page size and 16MB parge page size
+ * We don't need all the bits, but this seems to work.
+ * vpn cover upto 65 bits of va. (0...65) and we need
+ * 56..62 bits of va.
+ */
+ va |= ((vpn >> 2) & 0xfe);
+ }
va |= 1; /* L */
asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
: : "r"(va) : "memory");
@@ -114,22 +142,22 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
}
-static inline void tlbie(unsigned long vpn, int psize, int apsize,
+static inline void tlbie(unsigned long vpn, int bpsize, int apsize,
int ssize, int local)
{
unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
if (use_local)
- use_local = mmu_psize_defs[psize].tlbiel;
+ use_local = mmu_psize_defs[bpsize].tlbiel;
if (lock_tlbie && !use_local)
raw_spin_lock(&native_tlbie_lock);
asm volatile("ptesync": : :"memory");
if (use_local) {
- __tlbiel(vpn, psize, apsize, ssize);
+ __tlbiel(vpn, bpsize, apsize, ssize);
asm volatile("ptesync": : :"memory");
} else {
- __tlbie(vpn, psize, apsize, ssize);
+ __tlbie(vpn, bpsize, apsize, ssize);
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
if (lock_tlbie && !use_local)
--
1.7.10
--
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next prev parent reply other threads:[~2013-02-21 16:47 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-21 16:47 [RFC PATCH -V2 00/21] THP support for PPC64 Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 01/21] powerpc: Use signed formatting when printing error Aneesh Kumar K.V
2013-02-22 5:00 ` Paul Mackerras
2013-02-21 16:47 ` [RFC PATCH -V2 02/21] powerpc: Save DAR and DSISR in pt_regs on MCE Aneesh Kumar K.V
2013-02-22 5:03 ` Paul Mackerras
2013-02-21 16:47 ` [RFC PATCH -V2 03/21] powerpc: Don't hard code the size of pte page Aneesh Kumar K.V
2013-02-22 5:06 ` Paul Mackerras
2013-02-23 16:17 ` Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 04/21] powerpc: Reduce the PTE_INDEX_SIZE Aneesh Kumar K.V
2013-02-22 5:07 ` Paul Mackerras
2013-02-21 16:47 ` [RFC PATCH -V2 05/21] powerpc: Reduce PTE table memory wastage Aneesh Kumar K.V
2013-02-22 0:32 ` David Gibson
2013-02-22 5:14 ` Aneesh Kumar K.V
2013-02-22 5:23 ` Paul Mackerras
2013-02-22 17:20 ` Aneesh Kumar K.V
2013-02-23 16:38 ` Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 06/21] powerpc: Add size argument to pgtable_cache_add Aneesh Kumar K.V
2013-02-22 5:27 ` Paul Mackerras
2013-02-21 16:47 ` [RFC PATCH -V2 07/21] powerpc: Use encode avpn where we need only avpn values Aneesh Kumar K.V
2013-02-22 5:28 ` Paul Mackerras
2013-02-21 16:47 ` [RFC PATCH -V2 08/21] powerpc: Decode the pte-lp-encoding bits correctly Aneesh Kumar K.V
2013-02-22 5:37 ` Paul Mackerras
2013-02-24 16:51 ` Aneesh Kumar K.V
2013-02-24 17:45 ` Aneesh Kumar K.V
2013-02-21 16:47 ` Aneesh Kumar K.V [this message]
2013-02-21 16:47 ` [RFC PATCH -V2 10/21] powerpc: print both base and actual page size on hash failure Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 11/21] powerpc: Print page size info during boot Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 12/21] powerpc: Fix hpte_decode to use the correct decoding for page sizes Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 13/21] mm/THP: HPAGE_SHIFT is not a #define on some arch Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 14/21] mm/THP: Add pmd args to pgtable deposit and withdraw APIs Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 15/21] mm/THP: support for zerout withdraw Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 16/21] powerpc/THP: Implement transparent huge pages for ppc64 Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 17/21] powerpc/THP: Differentiate THP PMD entries from HUGETLB PMD entries Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 18/21] powerpc/THP: Add code to handle HPTE faults for large pages Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 19/21] powerpc/THP: hypervisor require few WIMG bit set Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 20/21] powerpc/THP: get_user_pages_fast changes Aneesh Kumar K.V
2013-02-21 16:47 ` [RFC PATCH -V2 21/21] powerpc/THP: Enable THP on PPC64 Aneesh Kumar K.V
2013-03-21 8:17 ` [RFC PATCH -V2 00/21] THP support for PPC64 Simon Jeons
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