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From: Toshi Kani <toshi.kani@hp.com>
To: bp@alien8.de, hpa@zytor.com, tglx@linutronix.de,
	mingo@redhat.com, akpm@linux-foundation.org, arnd@arndb.de
Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, x86@kernel.org,
	linux-nvdimm@lists.01.org, jgross@suse.com,
	stefan.bader@canonical.com, luto@amacapital.net, hmh@hmh.eng.br,
	yigal@plexistor.com, konrad.wilk@oracle.com, Elliott@hp.com,
	mcgrof@suse.com, hch@lst.de, Toshi Kani <toshi.kani@hp.com>
Subject: [PATCH v12 1/10] x86, mm, pat: Set WT to PA7 slot of PAT MSR
Date: Mon,  1 Jun 2015 13:36:24 -0600	[thread overview]
Message-ID: <1433187393-22688-2-git-send-email-toshi.kani@hp.com> (raw)
In-Reply-To: <1433187393-22688-1-git-send-email-toshi.kani@hp.com>

This patch sets WT to the PA7 slot in the PAT MSR when the processor
is not affected by the PAT errata.  The PA7 slot is chosen to improve
robustness in the presence of errata that might cause the high PAT bit
to be ignored.  This way a buggy PA7 slot access will hit the PA3 slot,
which is UC, so at worst we lose performance without causing a correctness
issue.

The following Intel processors are affected by the PAT errata.

   errata               cpuid
   ----------------------------------------------------
   Pentium 2, A52       family 0x6, model 0x5
   Pentium 3, E27       family 0x6, model 0x7, 0x8
   Pentium 3 Xenon, G26 family 0x6, model 0x7, 0x8, 0xa
   Pentium M, Y26       family 0x6, model 0x9
   Pentium M 90nm, X9   family 0x6, model 0xd
   Pentium 4, N46       family 0xf, model 0x0

Instead of making sharp boundary checks, this patch makes conservative
checks to exclude all Pentium 2, 3, M and 4 family processors.  For
such processors, _PAGE_CACHE_MODE_WT is redirected to UC- per the
default setup in __cachemode2pte_tbl[].

Signed-off-by: Toshi Kani <toshi.kani@hp.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/mm/pat.c |   57 ++++++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 49 insertions(+), 8 deletions(-)

diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index f89e460..83af01a 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -235,6 +235,7 @@ static void pat_ap_init(u64 pat)
 void pat_init(void)
 {
 	u64 pat;
+	struct cpuinfo_x86 *c = &boot_cpu_data;
 
 	if (!pat_enabled()) {
 		/*
@@ -259,21 +260,61 @@ void pat_init(void)
 		 */
 		pat = PAT(0, WB) | PAT(1, WT) | PAT(2, UC_MINUS) | PAT(3, UC) |
 		      PAT(4, WB) | PAT(5, WT) | PAT(6, UC_MINUS) | PAT(7, UC);
-	} else {
+
+	} else if ((c->x86_vendor == X86_VENDOR_INTEL) &&
+		   (((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||
+		    ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) {
 		/*
-		 * PTE encoding used in Linux:
+		 * PAT support with the lower four entries. Intel Pentium 2,
+		 * 3, M, and 4 are affected by PAT errata, which makes the
+		 * upper four entries unusable.  We do not use the upper four
+		 * entries for all the affected processor families for safe.
+		 *
+		 *  PTE encoding used in Linux:
 		 *      PAT
 		 *      |PCD
-		 *      ||PWT
-		 *      |||
-		 *      000 WB          _PAGE_CACHE_WB
-		 *      001 WC          _PAGE_CACHE_WC
-		 *      010 UC-         _PAGE_CACHE_UC_MINUS
-		 *      011 UC          _PAGE_CACHE_UC
+		 *      ||PWT  PAT
+		 *      |||    slot
+		 *      000    0    WB : _PAGE_CACHE_MODE_WB
+		 *      001    1    WC : _PAGE_CACHE_MODE_WC
+		 *      010    2    UC-: _PAGE_CACHE_MODE_UC_MINUS
+		 *      011    3    UC : _PAGE_CACHE_MODE_UC
 		 * PAT bit unused
+		 *
+		 * NOTE: When WT or WP is used, it is redirected to UC- per
+		 * the default setup in __cachemode2pte_tbl[].
 		 */
 		pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
 		      PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
+	} else {
+		/*
+		 * PAT full support.  We put WT in slot 7 to improve
+		 * robustness in the presence of errata that might cause
+		 * the high PAT bit to be ignored.  This way a buggy slot 7
+		 * access will hit slot 3, and slot 3 is UC, so at worst
+		 * we lose performance without causing a correctness issue.
+		 * Pentium 4 erratum N46 is an example of such an erratum,
+		 * although we try not to use PAT at all on affected CPUs.
+		 *
+		 *  PTE encoding used in Linux:
+		 *      PAT
+		 *      |PCD
+		 *      ||PWT  PAT
+		 *      |||    slot
+		 *      000    0    WB : _PAGE_CACHE_MODE_WB
+		 *      001    1    WC : _PAGE_CACHE_MODE_WC
+		 *      010    2    UC-: _PAGE_CACHE_MODE_UC_MINUS
+		 *      011    3    UC : _PAGE_CACHE_MODE_UC
+		 *      100    4    WB : Reserved
+		 *      101    5    WC : Reserved
+		 *      110    6    UC-: Reserved
+		 *      111    7    WT : _PAGE_CACHE_MODE_WT
+		 *
+		 * The reserved slots are unused, but mapped to their
+		 * corresponding types in the presence of PAT errata.
+		 */
+		pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
+		      PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, WT);
 	}
 
 	if (!boot_cpu_done) {

--
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  reply	other threads:[~2015-06-01 19:56 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-01 19:36 [PATCH v12 0/10] Support Write-Through mapping on x86 Toshi Kani
2015-06-01 19:36 ` Toshi Kani [this message]
2015-06-01 19:36 ` [PATCH v12 2/10] x86, mm, pat: Change reserve_memtype() for WT Toshi Kani
2015-06-01 19:36 ` [PATCH v12 3/10] x86, asm: Change is_new_memtype_allowed() " Toshi Kani
2015-06-01 19:36 ` [PATCH v12 4/10] x86, mm, asm-gen: Add ioremap_wt() " Toshi Kani
2015-06-01 19:36 ` [PATCH v12 5/10] arch/*/asm/io.h: Add ioremap_wt() to all architectures Toshi Kani
2015-06-01 19:36 ` [PATCH v12 6/10] video/fbdev, asm/io.h: Remove ioremap_writethrough() Toshi Kani
2015-06-02  7:06   ` Geert Uytterhoeven
2015-06-01 19:36 ` [PATCH v12 7/10] x86, mm, pat: Add pgprot_writethrough() for WT Toshi Kani
2015-06-01 19:36 ` [PATCH v12 08/10] x86, mm, asm: Add WT support to set_page_memtype() Toshi Kani
2015-06-01 19:36 ` [PATCH v12 09/10] x86, mm: Add set_memory_wt() for WT Toshi Kani
2015-06-01 19:36 ` [PATCH v12 10/10] drivers/block/pmem: Map NVDIMM with ioremap_wt() Toshi Kani
2015-06-02 16:21 ` [PATCH v12 0/10] Support Write-Through mapping on x86 Luis R. Rodriguez
2015-06-02 18:46   ` Toshi Kani
2015-06-02 19:43     ` Luis R. Rodriguez
2015-06-02 19:50       ` Andy Lutomirski
2015-06-02 20:01         ` Luis R. Rodriguez

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