From: Joerg Roedel <joro@8bytes.org>
To: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@kernel.org>, "H . Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org,
Linus Torvalds <torvalds@linux-foundation.org>,
Andy Lutomirski <luto@kernel.org>,
Dave Hansen <dave.hansen@intel.com>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Juergen Gross <jgross@suse.com>,
Peter Zijlstra <peterz@infradead.org>,
Borislav Petkov <bp@alien8.de>, Jiri Kosina <jkosina@suse.cz>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Brian Gerst <brgerst@gmail.com>,
David Laight <David.Laight@aculab.com>,
Denys Vlasenko <dvlasenk@redhat.com>,
Eduardo Valentin <eduval@amazon.com>,
Greg KH <gregkh@linuxfoundation.org>,
Will Deacon <will.deacon@arm.com>,
aliguori@amazon.com, daniel.gruss@iaik.tugraz.at,
hughd@google.com, keescook@google.com,
Andrea Arcangeli <aarcange@redhat.com>,
Waiman Long <llong@redhat.com>, Pavel Machek <pavel@ucw.cz>,
"David H . Gutteridge" <dhgutteridge@sympatico.ca>,
jroedel@suse.de, joro@8bytes.org
Subject: [PATCH 32/35] x86/ldt: Enable LDT user-mapping for PAE
Date: Mon, 16 Apr 2018 17:25:20 +0200 [thread overview]
Message-ID: <1523892323-14741-33-git-send-email-joro@8bytes.org> (raw)
In-Reply-To: <1523892323-14741-1-git-send-email-joro@8bytes.org>
From: Joerg Roedel <jroedel@suse.de>
This adds the needed special case for PAE to get the LDT
mapped into the user page-table when PTI is enabled. The big
difference to the other paging modes is that we don't have a
full top-level PGD entry available for the LDT, but only PMD
entry.
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
arch/x86/include/asm/mmu_context.h | 5 ----
arch/x86/kernel/ldt.c | 53 ++++++++++++++++++++++++++++++++++++++
2 files changed, 53 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index 57e3785..28b2376 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -71,12 +71,7 @@ struct ldt_struct {
static inline void *ldt_slot_va(int slot)
{
-#ifdef CONFIG_X86_64
return (void *)(LDT_BASE_ADDR + LDT_SLOT_STRIDE * slot);
-#else
- BUG();
- return (void *)fix_to_virt(FIX_HOLE);
-#endif
}
/*
diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c
index e68ce37..da80296 100644
--- a/arch/x86/kernel/ldt.c
+++ b/arch/x86/kernel/ldt.c
@@ -126,6 +126,57 @@ static void do_sanity_check(struct mm_struct *mm,
}
}
+#ifdef CONFIG_X86_PAE
+
+static pmd_t *pgd_to_pmd_walk(pgd_t *pgd, unsigned long va)
+{
+ p4d_t *p4d;
+ pud_t *pud;
+
+ if (pgd->pgd == 0)
+ return NULL;
+
+ p4d = p4d_offset(pgd, va);
+ if (p4d_none(*p4d))
+ return NULL;
+
+ pud = pud_offset(p4d, va);
+ if (pud_none(*pud))
+ return NULL;
+
+ return pmd_offset(pud, va);
+}
+
+static void map_ldt_struct_to_user(struct mm_struct *mm)
+{
+ pgd_t *k_pgd = pgd_offset(mm, LDT_BASE_ADDR);
+ pgd_t *u_pgd = kernel_to_user_pgdp(k_pgd);
+ pmd_t *k_pmd, *u_pmd;
+
+ k_pmd = pgd_to_pmd_walk(k_pgd, LDT_BASE_ADDR);
+ u_pmd = pgd_to_pmd_walk(u_pgd, LDT_BASE_ADDR);
+
+ if (static_cpu_has(X86_FEATURE_PTI) && !mm->context.ldt)
+ set_pmd(u_pmd, *k_pmd);
+}
+
+static void sanity_check_ldt_mapping(struct mm_struct *mm)
+{
+ pgd_t *k_pgd = pgd_offset(mm, LDT_BASE_ADDR);
+ pgd_t *u_pgd = kernel_to_user_pgdp(k_pgd);
+ bool had_kernel, had_user;
+ pmd_t *k_pmd, *u_pmd;
+
+ k_pmd = pgd_to_pmd_walk(k_pgd, LDT_BASE_ADDR);
+ u_pmd = pgd_to_pmd_walk(u_pgd, LDT_BASE_ADDR);
+ had_kernel = (k_pmd->pmd != 0);
+ had_user = (u_pmd->pmd != 0);
+
+ do_sanity_check(mm, had_kernel, had_user);
+}
+
+#else /* !CONFIG_X86_PAE */
+
static void map_ldt_struct_to_user(struct mm_struct *mm)
{
pgd_t *pgd = pgd_offset(mm, LDT_BASE_ADDR);
@@ -143,6 +194,8 @@ static void sanity_check_ldt_mapping(struct mm_struct *mm)
do_sanity_check(mm, had_kernel, had_user);
}
+#endif /* CONFIG_X86_PAE */
+
/*
* If PTI is enabled, this maps the LDT into the kernelmode and
* usermode tables for the given mm.
--
2.7.4
next prev parent reply other threads:[~2018-04-16 15:25 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-16 15:24 [PATCH 00/35 v5] PTI support for x32 Joerg Roedel
2018-04-16 15:24 ` [PATCH 01/35] x86/asm-offsets: Move TSS_sp0 and TSS_sp1 to asm-offsets.c Joerg Roedel
2018-04-16 15:24 ` [PATCH 02/35] x86/entry/32: Rename TSS_sysenter_sp0 to TSS_entry_stack Joerg Roedel
2018-04-16 15:24 ` [PATCH 03/35] x86/entry/32: Load task stack from x86_tss.sp1 in SYSENTER handler Joerg Roedel
2018-04-18 23:26 ` Andi Kleen
2018-04-19 0:02 ` Linus Torvalds
2018-04-19 0:38 ` Andi Kleen
2018-04-19 0:44 ` Andy Lutomirski
2018-04-19 9:01 ` David Laight
2018-04-16 15:24 ` [PATCH 04/35] x86/entry/32: Put ESPFIX code into a macro Joerg Roedel
2018-04-16 15:24 ` [PATCH 05/35] x86/entry/32: Unshare NMI return path Joerg Roedel
2018-04-16 15:24 ` [PATCH 06/35] x86/entry/32: Split off return-to-kernel path Joerg Roedel
2018-04-16 15:24 ` [PATCH 07/35] x86/entry/32: Enter the kernel via trampoline stack Joerg Roedel
2018-04-16 15:24 ` [PATCH 08/35] x86/entry/32: Leave " Joerg Roedel
2018-04-16 15:24 ` [PATCH 09/35] x86/entry/32: Introduce SAVE_ALL_NMI and RESTORE_ALL_NMI Joerg Roedel
2018-04-16 15:24 ` [PATCH 10/35] x86/entry/32: Handle Entry from Kernel-Mode on Entry-Stack Joerg Roedel
2018-04-16 15:24 ` [PATCH 11/35] x86/entry/32: Simplify debug entry point Joerg Roedel
2018-04-16 15:25 ` [PATCH 12/35] x86/32: Use tss.sp1 as cpu_current_top_of_stack Joerg Roedel
2018-04-16 15:25 ` [PATCH 13/35] x86/entry/32: Add PTI cr3 switch to non-NMI entry/exit points Joerg Roedel
2018-04-16 15:25 ` [PATCH 14/35] x86/entry/32: Add PTI cr3 switches to NMI handler code Joerg Roedel
2018-04-16 15:25 ` [PATCH 15/35] x86/pgtable: Rename pti_set_user_pgd to pti_set_user_pgtbl Joerg Roedel
2018-04-16 15:25 ` [PATCH 16/35] x86/pgtable/pae: Unshare kernel PMDs when PTI is enabled Joerg Roedel
2018-04-16 15:25 ` [PATCH 17/35] x86/pgtable/32: Allocate 8k page-tables " Joerg Roedel
2018-04-16 15:25 ` [PATCH 18/35] x86/pgtable: Move pgdp kernel/user conversion functions to pgtable.h Joerg Roedel
2018-04-16 15:25 ` [PATCH 19/35] x86/pgtable: Move pti_set_user_pgtbl() " Joerg Roedel
2018-04-16 15:25 ` [PATCH 20/35] x86/pgtable: Move two more functions from pgtable_64.h " Joerg Roedel
2018-04-16 15:25 ` [PATCH 21/35] x86/mm/pae: Populate valid user PGD entries Joerg Roedel
2018-04-16 15:25 ` [PATCH 22/35] x86/mm/pae: Populate the user page-table with user pgd's Joerg Roedel
2018-04-16 15:25 ` [PATCH 23/35] x86/mm/legacy: " Joerg Roedel
2018-04-16 15:25 ` [PATCH 24/35] x86/mm/pti: Add an overflow check to pti_clone_pmds() Joerg Roedel
2018-04-16 15:25 ` [PATCH 25/35] x86/mm/pti: Define X86_CR3_PTI_PCID_USER_BIT on x86_32 Joerg Roedel
2018-04-16 15:25 ` [PATCH 26/35] x86/mm/pti: Clone CPU_ENTRY_AREA on PMD level " Joerg Roedel
2018-04-16 15:25 ` [PATCH 27/35] x86/mm/dump_pagetables: Define INIT_PGD Joerg Roedel
2018-04-16 15:25 ` [PATCH 28/35] x86/pgtable/pae: Use separate kernel PMDs for user page-table Joerg Roedel
2018-04-16 15:25 ` [PATCH 29/35] x86/ldt: Reserve address-space range on 32 bit for the LDT Joerg Roedel
2018-04-16 15:25 ` [PATCH 30/35] x86/ldt: Define LDT_END_ADDR Joerg Roedel
2018-04-16 15:25 ` [PATCH 31/35] x86/ldt: Split out sanity check in map_ldt_struct() Joerg Roedel
2018-04-16 15:25 ` Joerg Roedel [this message]
2018-04-16 15:25 ` [PATCH 33/35] x86/pti: Allow CONFIG_PAGE_TABLE_ISOLATION for x86_32 Joerg Roedel
2018-04-16 15:25 ` [PATCH 34/35] x86/mm/pti: Add Warning when booting on a PCID capable CPU Joerg Roedel
2018-04-16 15:25 ` [PATCH 35/35] x86/entry/32: Add debug code to check entry/exit cr3 Joerg Roedel
2018-04-16 15:32 ` [PATCH 00/35 v5] PTI support for x32 Linus Torvalds
2018-04-16 16:01 ` Joerg Roedel
2018-04-16 16:13 ` Linus Torvalds
2018-04-18 7:35 ` Joerg Roedel
2018-04-16 17:57 ` H. Peter Anvin
-- strict thread matches above, loose matches on Subject: below --
2018-03-16 19:29 [PATCH 00/35 v4] " Joerg Roedel
2018-03-16 19:29 ` [PATCH 32/35] x86/ldt: Enable LDT user-mapping for PAE Joerg Roedel
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