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Wed, 16 Jun 2021 13:49:12 -0400 (EDT) Received: from mail03.efficios.com (mail03.efficios.com [167.114.26.124]) by mail.efficios.com (Postfix) with ESMTP id C392034A2F7; Wed, 16 Jun 2021 13:49:12 -0400 (EDT) Date: Wed, 16 Jun 2021 13:49:12 -0400 (EDT) From: Mathieu Desnoyers To: Andy Lutomirski Cc: x86 , Dave Hansen , linux-kernel , linux-mm , Andrew Morton , Nicholas Piggin , Peter Zijlstra Message-ID: <1612817467.9041.1623865752655.JavaMail.zimbra@efficios.com> In-Reply-To: <571b7e6b6a907e8a1ffc541c3f0005d347406fd0.1623813516.git.luto@kernel.org> References: <571b7e6b6a907e8a1ffc541c3f0005d347406fd0.1623813516.git.luto@kernel.org> Subject: Re: [PATCH 2/8] x86/mm: Handle unlazying membarrier core sync in the arch code MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Originating-IP: [167.114.26.124] X-Mailer: Zimbra 8.8.15_GA_4018 (ZimbraWebClient - FF89 (Linux)/8.8.15_GA_4026) Thread-Topic: x86/mm: Handle unlazying membarrier core sync in the arch code Thread-Index: xNxHDRQh7RLqFnf5iMUzvQDlhdKF9A== Authentication-Results: imf30.hostedemail.com; dkim=pass header.d=efficios.com header.s=default header.b=Q7qPgrVt; dmarc=pass (policy=none) header.from=efficios.com; spf=pass (imf30.hostedemail.com: domain of compudj@efficios.com designates 167.114.26.124 as permitted sender) smtp.mailfrom=compudj@efficios.com X-Stat-Signature: 1ozniypnyfoifunia8pdirxnj3ur4nre X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 93E0FE000255 X-HE-Tag: 1623865748-330631 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: ----- On Jun 15, 2021, at 11:21 PM, Andy Lutomirski luto@kernel.org wrote: [...] > @@ -473,16 +474,24 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct > mm_struct *next, [...] > @@ -510,16 +520,35 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct > mm_struct *next, > * If the TLB is up to date, just use it. > * The barrier synchronizes with the tlb_gen increment in > * the TLB shootdown code. > + * > + * As a future optimization opportunity, it's plausible > + * that the x86 memory model is strong enough that this > + * smp_mb() isn't needed. > */ > smp_mb(); > next_tlb_gen = atomic64_read(&next->context.tlb_gen); > if (this_cpu_read(cpu_tlbstate.ctxs[prev_asid].tlb_gen) == > - next_tlb_gen) > + next_tlb_gen) { > +#ifdef CONFIG_MEMBARRIER > + /* > + * We switched logical mm but we're not going to > + * write to CR3. We already did smp_mb() above, > + * but membarrier() might require a sync_core() > + * as well. > + */ > + if (unlikely(atomic_read(&next->membarrier_state) & > + MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE)) > + sync_core_before_usermode(); > +#endif > + > return; > + } [...] I find that mixing up preprocessor #ifdef and code logic hurts readability. Can you lift this into a static function within the same compile unit, and provides an empty implementation for the #else case ? Thanks, Mathieu prev->sched_class->task_dead(prev); -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com