Re: [RFC] [PATCH] Power Managed memory base enabling

[Mark Gross <mgross@linux.intel.com>]

On Tue, Mar 06, 2007 at 10:26:28AM +0900, KAMEZAWA Hiroyuki wrote:
> On Mon, 5 Mar 2007 10:18:26 -0800
> Mark Gross <mgross@linux.intel.com> wrote:
> 
> > It implements a convention on the 4 bytes of "Proximity Domain ID"
> > within the SRAT memory affinity structure as defined in ACPI3.0a.  If
> > bit 31 is set, then the memory range represented by that PXM is assumed
> > to be power managed.  We are working on defining a "standard" for
> > identifying such memory areas as power manageable and progress committee
> > based.  
> > 
> 
> This usage of bit 31 surprized me ;)
It was not my first choice but, adding a new flag bit takes the ACPI
standards committee to rubber stamp the notion.  That is a work in
progress.  The "architects" are pondering the nuances and implications
of this subject as we speak.  I'm sure something wonderful is forth
coming.

We are trying to get this code out there to enable OSV support for a
product with a first generation of power managed memory coming out this
summer in the ATCA form factor, the MPCBL0050.

Its my hope that this convention will not be disruptive or create too
much legacy once the ACPI committee catches up with this technology.
Its not expected to be a problem, as there is only one publicly
available platform rolling out this year with it.

> I think some vendor(sgi?) now using 4byte pxm...

I don't know if SGI has any system that use all 4 bytes of PXM.  I did
notice that until recently the ACPI code in Linux only used the first
byte of that field calling the upper bytes as reserved.  This should be
the first code in Linux to overload the meeting of this bit.


> no problem ? and othre OSs will handle this ?
>
I hope there is no problem. I posted this RFC to find out ;)

I don't know if any other OS's know about this type of memory.  

--mgross

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