From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Will Deacon <will.deacon@arm.com>,
Tim Chen <tim.c.chen@linux.intel.com>,
Ingo Molnar <mingo@elte.hu>,
Andrew Morton <akpm@linux-foundation.org>,
Thomas Gleixner <tglx@linutronix.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
linux-mm <linux-mm@kvack.org>,
"linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Waiman Long <waiman.long@hp.com>,
Andrea Arcangeli <aarcange@redhat.com>,
Alex Shi <alex.shi@linaro.org>, Andi Kleen <andi@firstfloor.org>,
Michel Lespinasse <walken@google.com>,
Davidlohr Bueso <davidlohr.bueso@hp.com>,
Matthew R Wilcox <matthew.r.wilcox@intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Rik van Riel <riel@redhat.com>,
Peter Hurley <peter@hurleysoftware.com>,
Raghavendra K T <raghavendra.kt@linux.vnet.ibm.com>,
George Spelvin <linux@horizon.com>, Arnd Bergmann <arnd@arndb.de>,
Aswin Chandramouleeswaran <aswin@hp.com>,
Scott J Norton <scott.norton@hp.com>,
"Figo.zhang" <figo1802@gmail.com>
Subject: Re: [PATCH v6 4/5] MCS Lock: Barrier corrections
Date: Mon, 25 Nov 2013 19:16:26 -0800 [thread overview]
Message-ID: <20131126031626.GE4138@linux.vnet.ibm.com> (raw)
In-Reply-To: <5293E37F.5020908@zytor.com>
On Mon, Nov 25, 2013 at 03:55:43PM -0800, H. Peter Anvin wrote:
> On 11/25/2013 10:02 AM, Paul E. McKenney wrote:
> >
> > I still do not believe that it does. Again, strangely enough.
> >
> > We need to ask someone in Intel that understands this all the way down
> > to the silicon. The guy I used to rely on for this no longer works
> > at Intel.
> >
> > Do you know someone who fits this description, or should I start sending
> > cold-call emails to various Intel contacts?
>
> Feel free to poke me if you need any help.
My biggest question is the definition of "Memory ordering obeys causality
(memory ordering respects transitive visibility)" in Section 3.2.2 of
the "Intel(R) 64 and IA-32 Architectures Developer's Manual: Vol. 3A"
dated March 2013 from:
http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html
I am guessing that is orders loads as well as stores, so that a load
is said to be "visible" to some other CPU once that CPU no longer has
the opportunity to affect the return value from the load. Is that a
reasonable interpretation?
More generally, is the model put forward by Sewell et al. in "x86-TSO:
A Rigorous and Usable Programmer's Model for x86 Multiprocessors"
accurate? This is on pages 4 and 5 here:
http://www.cl.cam.ac.uk/~pes20/weakmemory/cacm.pdf
Thanx, Paul
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next prev parent reply other threads:[~2013-11-26 3:16 UTC|newest]
Thread overview: 116+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1384885312.git.tim.c.chen@linux.intel.com>
2013-11-20 1:37 ` [PATCH v6 0/5] MCS Lock: MCS lock code cleanup and optimizations Tim Chen
2013-11-20 10:19 ` Will Deacon
2013-11-20 12:50 ` Paul E. McKenney
2013-11-20 17:00 ` Will Deacon
2013-11-20 17:14 ` Paul E. McKenney
2013-11-20 17:00 ` Tim Chen
2013-11-20 17:16 ` Paul E. McKenney
2013-11-20 1:37 ` [PATCH v6 1/5] MCS Lock: Restructure the MCS lock defines and locking code into its own file Tim Chen
2013-11-20 1:37 ` [PATCH v6 2/5] MCS Lock: optimizations and extra comments Tim Chen
2013-11-20 1:37 ` [PATCH v6 3/5] MCS Lock: Move mcs_lock/unlock function into its own file Tim Chen
2013-11-20 1:37 ` [PATCH v6 4/5] MCS Lock: Barrier corrections Tim Chen
2013-11-20 15:31 ` Paul E. McKenney
2013-11-20 15:46 ` Will Deacon
2013-11-20 17:14 ` Paul E. McKenney
2013-11-20 18:43 ` Tim Chen
2013-11-20 19:06 ` Paul E. McKenney
2013-11-20 20:36 ` Tim Chen
2013-11-20 21:44 ` Paul E. McKenney
2013-11-20 23:51 ` Tim Chen
2013-11-21 4:53 ` Paul E. McKenney
2013-11-21 10:17 ` Will Deacon
2013-11-21 13:16 ` Paul E. McKenney
2013-11-21 10:45 ` Peter Zijlstra
2013-11-21 13:18 ` Paul E. McKenney
2013-11-21 22:27 ` Linus Torvalds
2013-11-21 22:52 ` Paul E. McKenney
2013-11-22 0:09 ` Linus Torvalds
2013-11-22 4:08 ` Paul E. McKenney
2013-11-22 4:25 ` Linus Torvalds
2013-11-22 6:23 ` Paul E. McKenney
2013-11-22 15:16 ` Ingo Molnar
2013-11-22 18:49 ` Paul E. McKenney
2013-11-22 19:06 ` Linus Torvalds
2013-11-22 20:06 ` Paul E. McKenney
2013-11-22 20:09 ` Linus Torvalds
2013-11-22 20:37 ` Paul E. McKenney
2013-11-22 21:01 ` Linus Torvalds
2013-11-22 21:52 ` Paul E. McKenney
2013-11-22 22:19 ` Linus Torvalds
2013-11-23 0:25 ` Paul E. McKenney
2013-11-23 0:42 ` Linus Torvalds
2013-11-23 1:36 ` Paul E. McKenney
2013-11-23 2:11 ` Linus Torvalds
2013-11-23 4:05 ` Paul E. McKenney
2013-11-23 11:24 ` Ingo Molnar
2013-11-23 17:06 ` Paul E. McKenney
2013-11-26 12:02 ` Ingo Molnar
2013-11-26 19:28 ` Paul E. McKenney
2013-11-23 20:21 ` Linus Torvalds
2013-11-23 20:39 ` Linus Torvalds
2013-11-25 12:09 ` Peter Zijlstra
2013-11-25 17:18 ` Will Deacon
2013-11-25 17:56 ` Paul E. McKenney
2013-11-25 17:54 ` Paul E. McKenney
2013-11-23 21:29 ` Peter Zijlstra
2013-11-23 22:24 ` Linus Torvalds
2013-11-25 17:53 ` Paul E. McKenney
2013-11-25 18:21 ` Peter Zijlstra
2013-11-21 11:03 ` Peter Zijlstra
2013-11-21 12:56 ` Peter Zijlstra
2013-11-21 13:20 ` Paul E. McKenney
2013-11-21 17:25 ` Paul E. McKenney
2013-11-21 21:52 ` Peter Zijlstra
2013-11-21 22:18 ` Paul E. McKenney
2013-11-22 15:58 ` Peter Zijlstra
2013-11-22 18:26 ` Paul E. McKenney
2013-11-22 18:51 ` Peter Zijlstra
2013-11-22 18:59 ` Paul E. McKenney
2013-11-25 17:35 ` Peter Zijlstra
2013-11-25 18:02 ` Paul E. McKenney
2013-11-25 18:24 ` Peter Zijlstra
2013-11-25 18:34 ` Tim Chen
2013-11-25 18:27 ` Peter Zijlstra
2013-11-25 23:52 ` Paul E. McKenney
2013-11-26 9:59 ` Peter Zijlstra
2013-11-26 17:11 ` Paul E. McKenney
2013-11-26 17:18 ` Peter Zijlstra
2013-11-26 19:00 ` Linus Torvalds
2013-11-26 19:20 ` Paul E. McKenney
2013-11-26 19:32 ` Linus Torvalds
2013-11-26 22:51 ` Paul E. McKenney
2013-11-26 23:58 ` Linus Torvalds
2013-11-27 0:21 ` Thomas Gleixner
2013-11-27 0:39 ` Paul E. McKenney
2013-11-27 1:05 ` Linus Torvalds
2013-11-27 1:31 ` Paul E. McKenney
2013-11-27 10:16 ` Will Deacon
2013-11-27 17:11 ` Paul E. McKenney
2013-11-28 11:40 ` Will Deacon
2013-11-28 17:38 ` Paul E. McKenney
2013-11-28 18:03 ` Will Deacon
2013-11-28 18:27 ` Paul E. McKenney
2013-11-28 18:53 ` Will Deacon
2013-11-28 19:50 ` Paul E. McKenney
2013-11-29 16:17 ` Will Deacon
2013-11-29 16:44 ` Linus Torvalds
2013-11-29 18:18 ` Will Deacon
2013-11-30 17:38 ` Paul E. McKenney
2013-11-26 19:21 ` Peter Zijlstra
2013-11-27 16:58 ` Oleg Nesterov
2013-11-26 23:08 ` Benjamin Herrenschmidt
2013-11-25 23:55 ` H. Peter Anvin
2013-11-26 3:16 ` Paul E. McKenney [this message]
2013-11-27 0:46 ` H. Peter Anvin
2013-11-27 1:07 ` Linus Torvalds
2013-11-27 1:27 ` Paul E. McKenney
2013-11-27 2:59 ` H. Peter Anvin
2013-11-25 18:52 ` H. Peter Anvin
2013-11-25 22:58 ` Tim Chen
2013-11-25 23:28 ` H. Peter Anvin
2013-11-25 23:51 ` Paul E. McKenney
2013-11-25 23:36 ` Paul E. McKenney
2013-12-04 21:26 ` Andi Kleen
2013-12-04 22:07 ` Paul E. McKenney
2013-11-21 13:19 ` Paul E. McKenney
2013-11-20 1:37 ` [PATCH v6 5/5] MCS Lock: Allows for architecture specific mcs lock and unlock Tim Chen
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