From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qe0-f46.google.com (mail-qe0-f46.google.com [209.85.128.46]) by kanga.kvack.org (Postfix) with ESMTP id 15F546B0036 for ; Tue, 26 Nov 2013 20:31:32 -0500 (EST) Received: by mail-qe0-f46.google.com with SMTP id a11so6769978qen.33 for ; Tue, 26 Nov 2013 17:31:31 -0800 (PST) Received: from e36.co.us.ibm.com (e36.co.us.ibm.com. [32.97.110.154]) by mx.google.com with ESMTPS id u5si31847252qed.23.2013.11.26.17.31.30 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 26 Nov 2013 17:31:31 -0800 (PST) Received: from /spool/local by e36.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 26 Nov 2013 18:31:30 -0700 Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id 1CA2E1FF001A for ; Tue, 26 Nov 2013 18:31:08 -0700 (MST) Received: from d03av06.boulder.ibm.com (d03av06.boulder.ibm.com [9.17.195.245]) by b03cxnp08026.gho.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id rAQNTcR629098118 for ; Wed, 27 Nov 2013 00:29:38 +0100 Received: from d03av06.boulder.ibm.com (loopback [127.0.0.1]) by d03av06.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id rAR1YMew014558 for ; Tue, 26 Nov 2013 18:34:24 -0700 Date: Tue, 26 Nov 2013 17:31:24 -0800 From: "Paul E. McKenney" Subject: Re: [PATCH v6 4/5] MCS Lock: Barrier corrections Message-ID: <20131127013124.GK4137@linux.vnet.ibm.com> Reply-To: paulmck@linux.vnet.ibm.com References: <20131125182715.GG10022@twins.programming.kicks-ass.net> <20131125235252.GA4138@linux.vnet.ibm.com> <20131126095945.GI10022@twins.programming.kicks-ass.net> <20131126192003.GA4137@linux.vnet.ibm.com> <20131126225136.GG4137@linux.vnet.ibm.com> <20131127003904.GI4137@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: owner-linux-mm@kvack.org List-ID: To: Linus Torvalds Cc: Peter Zijlstra , Will Deacon , Tim Chen , Ingo Molnar , Andrew Morton , Thomas Gleixner , "linux-kernel@vger.kernel.org" , linux-mm , "linux-arch@vger.kernel.org" , Waiman Long , Andrea Arcangeli , Alex Shi , Andi Kleen , Michel Lespinasse , Davidlohr Bueso , Matthew R Wilcox , Dave Hansen , Rik van Riel , Peter Hurley , Raghavendra K T , George Spelvin , "H. Peter Anvin" , Arnd Bergmann , Aswin Chandramouleeswaran , Scott J Norton , "Figo.zhang" On Tue, Nov 26, 2013 at 05:05:14PM -0800, Linus Torvalds wrote: > On Tue, Nov 26, 2013 at 4:39 PM, Paul E. McKenney > wrote: > > > > Cross-CPU ordering. > > Ok, in that case I *suspect* we want an actual "spin_lock_mb()" > primitive, because if we go with the MCS lock approach, it's quite > possible that we find cases where the fast-case is already a barrier > (like it is on x86 by virtue of the locked instruction) but the MCS > case then is not. And then a separate barrier wouldn't be able to make > that kind of judgement. > > Or maybe we don't care enough. It *sounds* like on x86, we do probably > already get the cross-cpu case for free, and on other architectures we > may always need the memory barrier, so maybe the whole > "mb_after_spin_lock()" thing is fine. > > Ugh. Indeed! I don't know any way to deal with it other than enumerating the architectures and checking each. My first cut at that was earlier in this thread. Thanx, Paul -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org