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Date: Wed, 4 Dec 2013 22:26:13 +0100
From: Andi Kleen <andi@firstfloor.org>
Subject: Re: [PATCH v6 4/5] MCS Lock: Barrier corrections
Message-ID: <20131204212613.GA21717@two.firstfloor.org>
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To: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>, Will Deacon <will.deacon@arm.com>, Tim Chen <tim.c.chen@linux.intel.com>, Ingo Molnar <mingo@elte.hu>, Andrew Morton <akpm@linux-foundation.org>, Thomas Gleixner <tglx@linutronix.de>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, linux-mm <linux-mm@kvack.org>, "linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>, Linus Torvalds <torvalds@linux-foundation.org>, Waiman Long <waiman.long@hp.com>, Andrea Arcangeli <aarcange@redhat.com>, Alex Shi <alex.shi@linaro.org>, Andi Kleen <andi@firstfloor.org>, Michel Lespinasse <walken@google.com>, Davidlohr Bueso <davidlohr.bueso@hp.com>, Matthew R Wilcox <matthew.r.wilcox@intel.com>, Dave Hansen <dave.hansen@intel.com>, Rik van Riel <riel@redhat.com>, Peter Hurley <peter@hurleysoftware.com>, Raghavendra K T <raghavendra.kt@linux.vnet.ibm.com>, George Spelvin <linux@horizon.com>, "H. Peter Anvin" <hpa@zytor.com>, Arnd Bergmann <arnd@arndb.de>, Aswin Chandramouleeswaran <aswin@hp.com>, Scott J Norton <scott.norton@hp.com>, "Figo.zhang" <figo1802@gmail.com>

> Let's apply the Intel manual to the earlier example:
> 
> 	CPU 0		CPU 1			CPU 2
> 	-----		-----			-----
> 	x = 1;		r1 = SLA(lock);		y = 1;
> 	SSR(lock, 1);	r2 = y;			smp_mb();
> 						r3 = x;
> 
> 	assert(!(r1 == 1 && r2 == 0 && r3 == 0));

Hi Paul,

We discussed this example with CPU architects and they
agreed that it is valid to rely on (r1 == 1 && r2 == 0 && r3 == 0)
never happening.

So the MCS code is good without additional barriers.

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only.

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