From: Ingo Molnar <mingo@kernel.org>
To: Mel Gorman <mgorman@suse.de>
Cc: Alex Shi <alex.shi@linaro.org>, H Peter Anvin <hpa@zytor.com>,
Linux-X86 <x86@kernel.org>, Linux-MM <linux-mm@kvack.org>,
LKML <linux-kernel@vger.kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Andrew Morton <akpm@linux-foundation.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <a.p.zijlstra@chello.nl>
Subject: Re: [PATCH 2/3] x86: mm: Change tlb_flushall_shift for IvyBridge
Date: Thu, 12 Dec 2013 14:13:09 +0100 [thread overview]
Message-ID: <20131212131309.GD5806@gmail.com> (raw)
In-Reply-To: <1386849309-22584-3-git-send-email-mgorman@suse.de>
* Mel Gorman <mgorman@suse.de> wrote:
> There was a large performance regression that was bisected to commit 611ae8e3
> (x86/tlb: enable tlb flush range support for x86). This patch simply changes
> the default balance point between a local and global flush for IvyBridge.
>
> Signed-off-by: Mel Gorman <mgorman@suse.de>
> ---
> arch/x86/kernel/cpu/intel.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index dc1ec0d..2d93753 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -627,7 +627,7 @@ static void intel_tlb_flushall_shift_set(struct cpuinfo_x86 *c)
> tlb_flushall_shift = 5;
> break;
> case 0x63a: /* Ivybridge */
> - tlb_flushall_shift = 1;
> + tlb_flushall_shift = 2;
> break;
I'd not be surprised if other CPU models showed similar weaknesses
under ebizzy as well.
I don't particularly like the tuning aspect of the whole feature: the
tunings are model specific and they seem to come out of thin air,
without explicit measurements visible.
In particular the first commit that added this optimization:
commit c4211f42d3e66875298a5e26a75109878c80f15b
Date: Thu Jun 28 09:02:19 2012 +0800
x86/tlb: add tlb_flushall_shift for specific CPU
already had these magic tunings, with no explanation about what kind
of measurement was done to back up those tunings.
I don't think this is acceptable and until this is cleared up I think
we might be better off turning off this feature altogether, or making
a constant, very low tuning point.
The original code came via:
611ae8e3f520 x86/tlb: enable tlb flush range support for x86
which references a couple of benchmarks, in particular a
micro-benchmark:
My micro benchmark 'mummap' http://lkml.org/lkml/2012/5/17/59
show that the random memory access on other CPU has 0~50% speed up
on a 2P * 4cores * HT NHM EP while do 'munmap'.
if the tunings were done with the micro-benchmark then I think they
are bogus, because AFAICS it does not measure the adversarial case of
the optimization.
So I'd say at minimum we need to remove the per model tunings, and
need to use very conservative defaults, to make sure we don't slow
down reasonable workloads.
( In theory madvise() could give us information about the usage
pattern of the vma - but in practice madvise() is rarely used and I
doubt ebizzy or other real-world apps are using it, so it's
meaningless. )
Thanks,
Ingo
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next prev parent reply other threads:[~2013-12-12 13:13 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-12 11:55 [RFC PATCH 0/3] Fix ebizzy performance regression on IvyBridge due to X86 TLB range flush Mel Gorman
2013-12-12 11:55 ` [PATCH 1/3] x86: mm: Clean up inconsistencies when flushing TLB ranges Mel Gorman
2013-12-12 13:59 ` Alex Shi
2013-12-12 23:53 ` Mel Gorman
2013-12-12 11:55 ` [PATCH 2/3] x86: mm: Change tlb_flushall_shift for IvyBridge Mel Gorman
2013-12-12 13:13 ` Ingo Molnar [this message]
2013-12-12 13:38 ` Alex Shi
2013-12-12 14:11 ` Ingo Molnar
2013-12-13 1:02 ` Alex Shi
2013-12-13 2:11 ` Alex Shi
2013-12-13 13:43 ` Ingo Molnar
2013-12-14 11:01 ` Alex Shi
2013-12-14 14:19 ` Peter Zijlstra
2013-12-14 14:27 ` Peter Zijlstra
2013-12-16 13:59 ` Ingo Molnar
2013-12-17 11:59 ` Alex Shi
2013-12-17 13:14 ` Ingo Molnar
2013-12-16 8:26 ` Alex Shi
2013-12-16 10:06 ` Peter Zijlstra
2013-12-12 13:45 ` Alex Shi
2013-12-12 11:55 ` [PATCH 3/3] x86: mm: Account for the of CPUs that must be flushed during a TLB range flush Mel Gorman
2013-12-12 13:41 ` Alex Shi
2013-12-12 13:01 ` [RFC PATCH 0/3] Fix ebizzy performance regression on IvyBridge due to X86 " Ingo Molnar
2013-12-12 14:40 ` Mel Gorman
2013-12-13 13:35 ` Ingo Molnar
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