Re: [PATCH 0/3] TLB flush multiple pages per IPI v5

[Mel Gorman <mgorman@suse.de>]

On Tue, Jun 09, 2015 at 02:54:01PM -0700, Linus Torvalds wrote:
> On Tue, Jun 9, 2015 at 2:14 PM, Dave Hansen <dave.hansen@intel.com> wrote:
> >
> > The 0 cycle TLB miss was also interesting.  It goes back up to something
> > reasonable if I put the mb()/mfence's back.
> 
> So I've said it before, and I'll say it again: Intel does really well
> on TLB fills.
> 
> The reason is partly historical, with Win95 doing a ton of TLB
> invalidation (I think every single GDI call ended up invalidating the
> TLB, so under some important Windows benchmarks of the time, you
> literally had a TLB flush every 10k instructions!).
> 
> But partly it is because people are wrong in thinking that TLB fills
> have to be slow. There's a lot of complete garbage RISC machines where
> the TLB fill took forever, because in the name of simplicity it would
> stop the pipeline and often be done in SW.
> 
> The zero-cycle TLB fill is obviously a bit optimistic, but at the same
> time it's not completely insane. TLB fills can be prefetched, and the
> table walker can hit the cache, if you do them right. And Intel mostly
> does.
> 
> So the normal full (non-global) TLB fill really is fairly cheap. It's
> been optimized for, and the TLB gets re-filled fairly efficiently. I
> suspect that it's really the case that doing more than just a couple
> of single-tlb flushes is a complete waste of time: the flushing takes
> longer than re-filling the TLB well.
> 

I expect I'll do another revision of the series after 4.2-rc1 as it's way
too close to 4.1's release. When that happens, I'll drop patch 4 and leave
just the full non-global flush patch. In the event there is an architecture
that really cares about the refill cost or we find that there is a corner
case where the TLB refill hurts then patch 4 will be in the mail archives
to consider for rebase and testing.

-- 
Mel Gorman
SUSE Labs

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