[PATCH 0/4] Boot-time switching between 4- and 5-level paging for 4.15, Part 2

["Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>]

Hi Ingo,

Here's the second bunch of patches that prepare kernel to boot-time switching
between paging modes.

It's a small one. I hope we can get it in quick. :)

I include the zsmalloc patch again. We need something to address the issue.
If we would find a better solution, we can come back to the topic and
rework it.

Apart from zsmalloc patch, the patchset includes changes to decompression
code. I reworked these patches. They are split not exactly the way you've
described before, but I hope it's sensible anyway.

Please review and consider applying.

Kirill A. Shutemov (4):
  mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS
  x86/boot/compressed/64: Detect and handle 5-level paging at boot-time
  x86/boot/compressed/64: Introduce place_trampoline()
  x86/boot/compressed/64: Handle 5-level paging boot if kernel is above 4G

 arch/x86/boot/compressed/head_64.S          | 99 ++++++++++++++++++++---------
 arch/x86/boot/compressed/pagetable.c        | 61 ++++++++++++++++++
 arch/x86/boot/compressed/pagetable.h        | 18 ++++++
 arch/x86/include/asm/pgtable-3level_types.h |  1 +
 arch/x86/include/asm/pgtable_64_types.h     |  2 +
 mm/zsmalloc.c                               | 13 ++--
 6 files changed, 158 insertions(+), 36 deletions(-)
 create mode 100644 arch/x86/boot/compressed/pagetable.h

-- 
2.14.2

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