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From: "Kirill A. Shutemov" <kirill@shutemov.name>
To: Ingo Molnar <mingo@kernel.org>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	Ingo Molnar <mingo@redhat.com>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Andy Lutomirski <luto@amacapital.net>,
	Cyrill Gorcunov <gorcunov@openvz.org>,
	Borislav Petkov <bp@suse.de>, Andi Kleen <ak@linux.intel.com>,
	linux-mm@kvack.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/4] x86/boot/compressed/64: Introduce place_trampoline()
Date: Fri, 10 Nov 2017 12:55:53 +0300	[thread overview]
Message-ID: <20171110095553.llbcmvaakn56mhzq@node.shutemov.name> (raw)
In-Reply-To: <20171110092812.ad2i6fj5wmdmheuf@gmail.com>

On Fri, Nov 10, 2017 at 10:28:12AM +0100, Ingo Molnar wrote:
> 
> * Ingo Molnar <mingo@kernel.org> wrote:
> 
> > > --- a/arch/x86/boot/compressed/head_64.S
> > > +++ b/arch/x86/boot/compressed/head_64.S
> > > @@ -315,6 +315,18 @@ ENTRY(startup_64)
> > >  	 * The first step is go into compatibility mode.
> > >  	 */
> > >  
> > > +	/*
> > > +	 * Find suitable place for trampoline and populate it.
> > > +	 * The address will be stored in RCX.
> > > +	 *
> > > +	 * RSI holds real mode data and need to be preserved across
> > > +	 * a function call.
> > > +	 */
> > > +	pushq	%rsi
> > > +	call	place_trampoline
> > > +	popq	%rsi
> > > +	movq	%rax, %rcx
> > > +
> > >  	/* Clear additional page table */
> > >  	leaq	lvl5_pgtable(%rbx), %rdi
> > >  	xorq	%rax, %rax
> > 
> > One request: it's always going to be fragile if the _only_ thing that uses the 
> > trampoline is the 5-level paging code.
> > 
> > Could we use the trampoline in the 4-level paging case too? It's not required, but 
> > would test much of the trampoline allocation and copying machinery - and the 
> > performance cost is negligible.
> 
> Note that right now the trampoline is pointless on 4-level setups, so there's 
> nothing to copy - but we could perhaps make it meaningful. But maybe it's not a 
> good idea.

Let me see how it will play out.

> One other detail I noticed:
> 
>         /* Bound size of trampoline code */
>         .org    lvl5_trampoline_src + LVL5_TRAMPOLINE_CODE_SIZE
> 
> will this generate a build error if the trampoline code exceeds 0x40?

Yes, this is the point. Just a failsafe if trampoline code would grew too
much.

-- 
 Kirill A. Shutemov

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  reply	other threads:[~2017-11-10  9:55 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-01 11:54 [PATCH 0/4] x86: 5-level related changes into decompression code Kirill A. Shutemov
2017-11-01 11:55 ` [PATCH 1/4] x86/boot/compressed/64: Compile pagetable.c unconditionally Kirill A. Shutemov
2017-11-10  9:12   ` Ingo Molnar
2017-11-10  9:25     ` Kirill A. Shutemov
2017-11-01 11:55 ` [PATCH 2/4] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time Kirill A. Shutemov
2017-11-10  9:13   ` Ingo Molnar
2017-11-01 11:55 ` [PATCH 3/4] x86/boot/compressed/64: Introduce place_trampoline() Kirill A. Shutemov
2017-11-10  9:14   ` Ingo Molnar
2017-11-10  9:52     ` Kirill A. Shutemov
2017-11-10  9:17   ` Ingo Molnar
2017-11-10  9:28     ` Ingo Molnar
2017-11-10  9:55       ` Kirill A. Shutemov [this message]
2017-11-10 12:46         ` Ingo Molnar
2017-11-10  9:29   ` Ingo Molnar
2017-11-10  9:57     ` Kirill A. Shutemov
2017-11-01 11:55 ` [PATCH 4/4] x86/boot/compressed/64: Handle 5-level paging boot if kernel is above 4G Kirill A. Shutemov
  -- strict thread matches above, loose matches on Subject: below --
2017-10-20 19:59 [PATCH 0/4] Boot-time switching between 4- and 5-level paging for 4.15, Part 2 Kirill A. Shutemov
2017-10-20 19:59 ` [PATCH 3/4] x86/boot/compressed/64: Introduce place_trampoline() Kirill A. Shutemov

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