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[192.55.52.115]) by mx.google.com with ESMTPS id n20si292453plp.294.2019.02.11.07.23.25 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Feb 2019 07:23:25 -0800 (PST) Received-SPF: pass (google.com: domain of keith.busch@intel.com designates 192.55.52.115 as permitted sender) client-ip=192.55.52.115; Authentication-Results: mx.google.com; spf=pass (google.com: domain of keith.busch@intel.com designates 192.55.52.115 as permitted sender) smtp.mailfrom=keith.busch@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Feb 2019 07:23:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,359,1544515200"; d="scan'208";a="274157759" Received: from unknown (HELO localhost.localdomain) ([10.232.112.69]) by orsmga004.jf.intel.com with ESMTP; 11 Feb 2019 07:23:24 -0800 Date: Mon, 11 Feb 2019 08:23:04 -0700 From: Keith Busch To: Jonathan Cameron Cc: Brice Goglin , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "linux-mm@kvack.org" , Greg Kroah-Hartman , Rafael Wysocki , "Hansen, Dave" , "Williams, Dan J" Subject: Re: [PATCHv4 10/13] node: Add memory caching attributes Message-ID: <20190211152303.GA4525@localhost.localdomain> References: <20190116175804.30196-1-keith.busch@intel.com> <20190116175804.30196-11-keith.busch@intel.com> <4a7d1c0c-c269-d7b2-11cb-88ad62b70a06@inria.fr> <20190210171958.00003ab2@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190210171958.00003ab2@huawei.com> User-Agent: Mutt/1.9.1 (2017-09-22) X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Sun, Feb 10, 2019 at 09:19:58AM -0800, Jonathan Cameron wrote: > On Sat, 9 Feb 2019 09:20:53 +0100 > Brice Goglin wrote: > > > Hello Keith > > > > Could we ever have a single side cache in front of two NUMA nodes ? I > > don't see a way to find that out in the current implementation. Would we > > have an "id" and/or "nodemap" bitmask in the sidecache structure ? > > This is certainly a possible thing for hardware to do. > > ACPI IIRC doesn't provide any means of representing that - your best > option is to represent it as two different entries, one for each of the > memory nodes. Interesting question of whether you would then claim > they were half as big each, or the full size. Of course, there are > other possible ways to get this info beyond HMAT, so perhaps the interface > should allow it to be exposed if available? HMAT doesn't do this, but I want this interface abstracted enough from HMAT to express whatever is necessary. The CPU cache is the closest existing exported attributes to this, and they provide "shared_cpu_list". To that end, I can export a "shared_node_list", though previous reviews strongly disliked multi-value sysfs entries. :( Would shared-node symlinks capture the need, and more acceptable? > Also, don't know if it's just me, but calling these sidecaches is > downright confusing. In ACPI at least they are always > specifically referred to as Memory Side Caches. > I'd argue there should even by a hyphen Memory-Side Caches, the point > being that that they are on the memory side of the interconnected > rather than the processor side. Of course an implementation > choice might be to put them off to the side (as implied by sidecaches) > in some sense, but it's not the only one. > > :) Now that you mention it, I agree "side" is ambiguous. Maybe call it "numa_cache" or "node_cache"?