From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91EC6C4CED1 for ; Thu, 3 Oct 2019 20:20:19 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 4613620862 for ; Thu, 3 Oct 2019 20:20:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4613620862 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=stgolabs.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id E7CFB6B0008; Thu, 3 Oct 2019 16:20:18 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id E2D026B000A; Thu, 3 Oct 2019 16:20:18 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id D1B308E0003; Thu, 3 Oct 2019 16:20:18 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0087.hostedemail.com [216.40.44.87]) by kanga.kvack.org (Postfix) with ESMTP id ADFFC6B0008 for ; Thu, 3 Oct 2019 16:20:18 -0400 (EDT) Received: from smtpin09.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay01.hostedemail.com (Postfix) with SMTP id 5AD80180AD7C3 for ; Thu, 3 Oct 2019 20:20:18 +0000 (UTC) X-FDA: 76003590516.09.beef81_29b06ad19e61 X-HE-Tag: beef81_29b06ad19e61 X-Filterd-Recvd-Size: 12013 Received: from mx1.suse.de (mx2.suse.de [195.135.220.15]) by imf24.hostedemail.com (Postfix) with ESMTP for ; Thu, 3 Oct 2019 20:20:17 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 61908B071; Thu, 3 Oct 2019 20:20:16 +0000 (UTC) From: Davidlohr Bueso To: akpm@linux-foundation.org Cc: walken@google.com, peterz@infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, dri-devel@lists.freedesktop.org, linux-rdma@vger.kernel.org, dave@stgolabs.net, Jerome Glisse , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Daniel Vetter , amd-gfx@lists.freedesktop.org, Davidlohr Bueso Subject: [PATCH 03/11] drm/amdgpu: convert amdgpu_vm_it to half closed intervals Date: Thu, 3 Oct 2019 13:18:50 -0700 Message-Id: <20191003201858.11666-4-dave@stgolabs.net> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191003201858.11666-1-dave@stgolabs.net> References: <20191003201858.11666-1-dave@stgolabs.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The amdgpu_vm interval tree really wants [a, b) intervals, not fully closed ones. As such convert it to use the new interval_tree_gen.h, and also rename the 'last' endpoint in the node to 'end', which is both a more suitable name for the half closed interval and also reduces the chances of missing a conversion when doing insertion or lookup. Cc: Jerome Glisse Cc: Alex Deucher Cc: "Christian K=C3=B6nig" Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Signed-off-by: Davidlohr Bueso --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 18 ++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 46 +++++++++++++++---------= ------ 6 files changed, 36 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_cs.c index 49b767b7238f..290bfe820890 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -756,7 +756,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_par= ser *p) } =20 if ((va_start + chunk_ib->ib_bytes) > - (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) { + m->end * AMDGPU_GPU_PAGE_SIZE) { DRM_ERROR("IB va_start+ib_bytes is invalid\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm= /amd/amdgpu/amdgpu_object.h index 7e99f6c58c48..60b73bc4d11a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -51,7 +51,7 @@ struct amdgpu_bo_va_mapping { struct list_head list; struct rb_node rb; uint64_t start; - uint64_t last; + uint64_t end; uint64_t __subtree_last; uint64_t offset; uint64_t flags; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/= amd/amdgpu/amdgpu_trace.h index 8227ebd0f511..c5b0e88d019c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -247,7 +247,7 @@ TRACE_EVENT(amdgpu_vm_bo_map, TP_STRUCT__entry( __field(struct amdgpu_bo *, bo) __field(long, start) - __field(long, last) + __field(long, end) __field(u64, offset) __field(u64, flags) ), @@ -255,12 +255,12 @@ TRACE_EVENT(amdgpu_vm_bo_map, TP_fast_assign( __entry->bo =3D bo_va ? bo_va->base.bo : NULL; __entry->start =3D mapping->start; - __entry->last =3D mapping->last; + __entry->end =3D mapping->end; __entry->offset =3D mapping->offset; __entry->flags =3D mapping->flags; ), - TP_printk("bo=3D%p, start=3D%lx, last=3D%lx, offset=3D%010llx, flag= s=3D%llx", - __entry->bo, __entry->start, __entry->last, + TP_printk("bo=3D%p, start=3D%lx, end=3D%lx, offset=3D%010llx, flags= =3D%llx", + __entry->bo, __entry->start, __entry->end, __entry->offset, __entry->flags) ); =20 @@ -271,7 +271,7 @@ TRACE_EVENT(amdgpu_vm_bo_unmap, TP_STRUCT__entry( __field(struct amdgpu_bo *, bo) __field(long, start) - __field(long, last) + __field(long, end) __field(u64, offset) __field(u64, flags) ), @@ -279,12 +279,12 @@ TRACE_EVENT(amdgpu_vm_bo_unmap, TP_fast_assign( __entry->bo =3D bo_va ? bo_va->base.bo : NULL; __entry->start =3D mapping->start; - __entry->last =3D mapping->last; + __entry->end =3D mapping->end; __entry->offset =3D mapping->offset; __entry->flags =3D mapping->flags; ), - TP_printk("bo=3D%p, start=3D%lx, last=3D%lx, offset=3D%010llx, flag= s=3D%llx", - __entry->bo, __entry->start, __entry->last, + TP_printk("bo=3D%p, start=3D%lx, end=3D%lx, offset=3D%010llx, flags= =3D%llx", + __entry->bo, __entry->start, __entry->end, __entry->offset, __entry->flags) ); =20 @@ -299,7 +299,7 @@ DECLARE_EVENT_CLASS(amdgpu_vm_mapping, =20 TP_fast_assign( __entry->soffset =3D mapping->start; - __entry->eoffset =3D mapping->last + 1; + __entry->eoffset =3D mapping->end; __entry->flags =3D mapping->flags; ), TP_printk("soffs=3D%010llx, eoffs=3D%010llx, flags=3D%llx", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/am= d/amdgpu/amdgpu_uvd.c index b2c364b8695f..8094dd0b0332 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -819,7 +819,7 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_c= tx *ctx) =20 start =3D amdgpu_bo_gpu_offset(bo); =20 - end =3D (mapping->last + 1 - mapping->start); + end =3D mapping->end - mapping->start; end =3D end * AMDGPU_GPU_PAGE_SIZE + start; =20 addr -=3D mapping->start * AMDGPU_GPU_PAGE_SIZE; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/am= d/amdgpu/amdgpu_vce.c index b70b3c45bb29..d6511bf446df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -642,8 +642,7 @@ static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parse= r *p, uint32_t ib_idx, return r; } =20 - if ((addr + (uint64_t)size) > - (mapping->last + 1) * AMDGPU_GPU_PAGE_SIZE) { + if ((addr + (uint64_t)size) > mapping->end * AMDGPU_GPU_PAGE_SIZE) { DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n", addr, lo, hi); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_vm.c index a2c797e34a29..2f618017617e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -26,7 +26,7 @@ * Jerome Glisse */ #include -#include +#include #include =20 #include @@ -58,13 +58,13 @@ */ =20 #define START(node) ((node)->start) -#define LAST(node) ((node)->last) +#define END(node) ((node)->end) =20 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtre= e_last, - START, LAST, static, amdgpu_vm_it) + START, END, static, amdgpu_vm_it) =20 #undef START -#undef LAST +#undef END =20 /** * struct amdgpu_prt_cb - Helper to disable partial resident texture fea= ture from a fence callback @@ -1616,7 +1616,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu= _device *adev, do { dma_addr_t *dma_addr =3D NULL; uint64_t max_entries; - uint64_t addr, last; + uint64_t addr, end; =20 if (nodes) { addr =3D nodes->start << PAGE_SHIFT; @@ -1654,21 +1654,21 @@ static int amdgpu_vm_bo_split_mapping(struct amdg= pu_device *adev, addr +=3D pfn << PAGE_SHIFT; } =20 - last =3D min((uint64_t)mapping->last, start + max_entries - 1); + end =3D min((uint64_t)mapping->end, start + max_entries); r =3D amdgpu_vm_bo_update_mapping(adev, vm, false, exclusive, - start, last, flags, addr, + start, end, flags, addr, dma_addr, fence); if (r) return r; =20 - pfn +=3D (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE; + pfn +=3D (end - start) / AMDGPU_GPU_PAGES_IN_CPU_PAGE; if (nodes && nodes->size =3D=3D pfn) { pfn =3D 0; ++nodes; } - start =3D last + 1; + start =3D end; =20 - } while (unlikely(start !=3D mapping->last + 1)); + } while (unlikely(start !=3D mapping->end)); =20 return 0; } @@ -1946,7 +1946,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *ade= v, init_pte_value =3D AMDGPU_PTE_DEFAULT_ATC; =20 r =3D amdgpu_vm_bo_update_mapping(adev, vm, false, NULL, - mapping->start, mapping->last, + mapping->start, mapping->end, init_pte_value, 0, NULL, &f); amdgpu_vm_free_mapping(adev, vm, mapping, f); if (r) { @@ -2129,7 +2129,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, return -EINVAL; =20 /* make sure object fit at this offset */ - eaddr =3D saddr + size - 1; + eaddr =3D saddr + size; if (saddr >=3D eaddr || (bo && offset + size > amdgpu_bo_size(bo))) return -EINVAL; @@ -2142,7 +2142,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, /* bo and tmp overlap, invalid addr */ dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, - tmp->start, tmp->last + 1); + tmp->start, tmp->end); return -EINVAL; } =20 @@ -2151,7 +2151,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, return -ENOMEM; =20 mapping->start =3D saddr; - mapping->last =3D eaddr; + mapping->end =3D eaddr; mapping->offset =3D offset; mapping->flags =3D flags; =20 @@ -2194,7 +2194,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *= adev, return -EINVAL; =20 /* make sure object fit at this offset */ - eaddr =3D saddr + size - 1; + eaddr =3D saddr + size; if (saddr >=3D eaddr || (bo && offset + size > amdgpu_bo_size(bo))) return -EINVAL; @@ -2214,7 +2214,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *= adev, eaddr /=3D AMDGPU_GPU_PAGE_SIZE; =20 mapping->start =3D saddr; - mapping->last =3D eaddr; + mapping->end =3D eaddr; mapping->offset =3D offset; mapping->flags =3D flags; =20 @@ -2299,7 +2299,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_devic= e *adev, LIST_HEAD(removed); uint64_t eaddr; =20 - eaddr =3D saddr + size - 1; + eaddr =3D saddr + size; saddr /=3D AMDGPU_GPU_PAGE_SIZE; eaddr /=3D AMDGPU_GPU_PAGE_SIZE; =20 @@ -2322,7 +2322,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_devic= e *adev, /* Remember mapping split at the start */ if (tmp->start < saddr) { before->start =3D tmp->start; - before->last =3D saddr - 1; + before->end =3D saddr; before->offset =3D tmp->offset; before->flags =3D tmp->flags; before->bo_va =3D tmp->bo_va; @@ -2330,9 +2330,9 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_devic= e *adev, } =20 /* Remember mapping split at the end */ - if (tmp->last > eaddr) { - after->start =3D eaddr + 1; - after->last =3D tmp->last; + if (tmp->end > eaddr) { + after->start =3D eaddr; + after->end =3D tmp->end; after->offset =3D tmp->offset; after->offset +=3D after->start - tmp->start; after->flags =3D tmp->flags; @@ -2353,8 +2353,8 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_devic= e *adev, =20 if (tmp->start < saddr) tmp->start =3D saddr; - if (tmp->last > eaddr) - tmp->last =3D eaddr; + if (tmp->end > eaddr) + tmp->end =3D eaddr; =20 tmp->bo_va =3D NULL; list_add(&tmp->list, &vm->freed); --=20 2.16.4