* Re: [PATCH v2 07/17] PCI: Clean up and document PM/reset delays
[not found] <20200302184429.12880-8-stanspas@amazon.com>
@ 2020-03-03 1:51 ` kbuild test robot
2020-03-03 2:54 ` kbuild test robot
1 sibling, 0 replies; 2+ messages in thread
From: kbuild test robot @ 2020-03-03 1:51 UTC (permalink / raw)
To: Stanislav Spassov; +Cc: kbuild-all, linux-pci, Linux Memory Management List
[-- Attachment #1: Type: text/plain, Size: 4578 bytes --]
Hi Stanislav,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9]
url: https://github.com/0day-ci/linux/commits/Stanislav-Spassov/Improve-PCI-device-post-reset-readiness-polling/20200303-043307
base: bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9
config: arm-multi_v5_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 7.5.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.5.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/pci/controller/pci-mvebu.c: In function 'mvebu_pcie_powerup':
>> drivers/pci/controller/pci-mvebu.c:930:22: error: 'PCI_PM_D3COLD_WAIT' undeclared (first use in this function); did you mean 'PCI_PM_D3HOT_DELAY'?
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
^~~~~~~~~~~~~~~~~~
PCI_PM_D3HOT_DELAY
drivers/pci/controller/pci-mvebu.c:930:22: note: each undeclared identifier is reported only once for each function it appears in
vim +930 drivers/pci/controller/pci-mvebu.c
49cb1f718360f8 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 915
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 916 /*
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 917 * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 918 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 919 * of the PCI Express Card Electromechanical Specification, 1.1.
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 920 */
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 921 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 922 {
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 923 int ret;
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 924
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 925 ret = clk_prepare_enable(port->clk);
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 926 if (ret < 0)
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 927 return ret;
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 928
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 929 if (port->reset_gpio) {
8ed81ec82a8c57 drivers/pci/host/pci-mvebu.c Lucas Stach 2017-02-02 @930 u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 931
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 932 of_property_read_u32(port->dn, "reset-delay-us",
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 933 &reset_udelay);
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 934
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 935 udelay(100);
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 936
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 937 gpiod_set_value_cansleep(port->reset_gpio, 0);
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 938 msleep(reset_udelay / 1000);
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 939 }
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 940
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 941 return 0;
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 942 }
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03 943
:::::: The code at line 930 was first introduced by commit
:::::: 8ed81ec82a8c57c3a6ad69b4c4d3e4801163c256 PCI: mvebu: Change delay after reset to the PCIe spec mandated 100ms
:::::: TO: Lucas Stach <l.stach@pengutronix.de>
:::::: CC: Bjorn Helgaas <bhelgaas@google.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 34127 bytes --]
^ permalink raw reply [flat|nested] 2+ messages in thread* Re: [PATCH v2 07/17] PCI: Clean up and document PM/reset delays
[not found] <20200302184429.12880-8-stanspas@amazon.com>
2020-03-03 1:51 ` [PATCH v2 07/17] PCI: Clean up and document PM/reset delays kbuild test robot
@ 2020-03-03 2:54 ` kbuild test robot
1 sibling, 0 replies; 2+ messages in thread
From: kbuild test robot @ 2020-03-03 2:54 UTC (permalink / raw)
To: Stanislav Spassov; +Cc: kbuild-all, linux-pci, Linux Memory Management List
[-- Attachment #1: Type: text/plain, Size: 15093 bytes --]
Hi Stanislav,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9]
url: https://github.com/0day-ci/linux/commits/Stanislav-Spassov/Improve-PCI-device-post-reset-readiness-polling/20200303-043307
base: bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 7.5.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.5.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/pci/controller/pci-aardvark.c: In function 'advk_pcie_setup_hw':
>> drivers/pci/controller/pci-aardvark.c:347:9: error: 'PCI_PM_D3COLD_WAIT' undeclared (first use in this function); did you mean 'PCI_PM_D3HOT_DELAY'?
msleep(PCI_PM_D3COLD_WAIT);
^~~~~~~~~~~~~~~~~~
PCI_PM_D3HOT_DELAY
drivers/pci/controller/pci-aardvark.c:347:9: note: each undeclared identifier is reported only once for each function it appears in
vim +347 drivers/pci/controller/pci-aardvark.c
364b3f1ff8f096 drivers/pci/controller/pci-aardvark.c Remi Pommarel 2019-05-22 255
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 256 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 257 {
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 258 u32 reg;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 259
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 260 /* Set to Direct mode */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 261 reg = advk_readl(pcie, CTRL_CONFIG_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 262 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 263 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 264 advk_writel(pcie, reg, CTRL_CONFIG_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 265
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 266 /* Set PCI global control register to RC mode */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 267 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 268 reg |= (IS_RC_MSK << IS_RC_SHIFT);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 269 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 270
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 271 /* Set Advanced Error Capabilities and Control PF0 register */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 272 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 273 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 274 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 275 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 276 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 277
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 278 /* Set PCIe Device Control and Status 1 PF0 register */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 279 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 280 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 281 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
fc31c4e347c9da drivers/pci/host/pci-aardvark.c Evan Wang 2018-04-06 282 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
fc31c4e347c9da drivers/pci/host/pci-aardvark.c Evan Wang 2018-04-06 283 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 284 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 285
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 286 /* Program PCIe Control 2 to disable strict ordering */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 287 reg = PCIE_CORE_CTRL2_RESERVED |
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 288 PCIE_CORE_CTRL2_TD_ENABLE;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 289 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 290
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 291 /* Set GEN2 */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 292 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 293 reg &= ~PCIE_GEN_SEL_MSK;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 294 reg |= SPEED_GEN_2;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 295 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 296
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 297 /* Set lane X1 */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 298 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 299 reg &= ~LANE_CNT_MSK;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 300 reg |= LANE_COUNT_1;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 301 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 302
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 303 /* Enable link training */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 304 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 305 reg |= LINK_TRAINING_EN;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 306 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 307
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 308 /* Enable MSI */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 309 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 310 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 311 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 312
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 313 /* Clear all interrupts */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 314 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 315 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 316 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 317
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 318 /* Disable All ISR0/1 Sources */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 319 reg = PCIE_ISR0_ALL_MASK;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 320 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 321 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 322
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 323 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 324
f6b6aefee70aa5 drivers/pci/controller/pci-aardvark.c Bjorn Helgaas 2019-05-30 325 /* Unmask all MSIs */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 326 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 327
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 328 /* Enable summary interrupt for GIC SPI source */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 329 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 330 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 331
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 332 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 333 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 334 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 335
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 336 /* Bypass the address window mapping for PIO */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 337 reg = advk_readl(pcie, PIO_CTRL);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 338 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 339 advk_writel(pcie, reg, PIO_CTRL);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 340
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel 2019-05-22 341 /*
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel 2019-05-22 342 * PERST# signal could have been asserted by pinctrl subsystem before
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel 2019-05-22 343 * probe() callback has been called, making the endpoint going into
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel 2019-05-22 344 * fundamental reset. As required by PCI Express spec a delay for at
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel 2019-05-22 345 * least 100ms after such a reset before link training is needed.
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel 2019-05-22 346 */
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel 2019-05-22 @347 msleep(PCI_PM_D3COLD_WAIT);
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel 2019-05-22 348
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 349 /* Start link training */
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 350 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 351 reg |= PCIE_CORE_LINK_TRAINING;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 352 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 353
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 354 advk_pcie_wait_for_link(pcie);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 355
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 356 reg = PCIE_CORE_LINK_L0S_ENTRY |
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 357 (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 358 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 359
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 360 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 361 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 362 PCIE_CORE_CMD_IO_ACCESS_EN |
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 363 PCIE_CORE_CMD_MEM_IO_REQ_EN;
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 364 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 365 }
8c39d710363c14 drivers/pci/host/pci-aardvark.c Thomas Petazzoni 2016-06-30 366
:::::: The code at line 347 was first introduced by commit
:::::: f4c7d053d7f77cd5c1a1ba7c7ce085ddba13d1d7 PCI: aardvark: Wait for endpoint to be ready before training link
:::::: TO: Remi Pommarel <repk@triplefau.lt>
:::::: CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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