From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75E0BC48BE8 for ; Wed, 16 Jun 2021 16:00:59 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 23EFC61164 for ; Wed, 16 Jun 2021 16:00:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 23EFC61164 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id AFB796B0036; Wed, 16 Jun 2021 12:00:58 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id AAB226B006E; Wed, 16 Jun 2021 12:00:58 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 94BC16B0070; Wed, 16 Jun 2021 12:00:58 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0097.hostedemail.com [216.40.44.97]) by kanga.kvack.org (Postfix) with ESMTP id 5E7566B0036 for ; Wed, 16 Jun 2021 12:00:58 -0400 (EDT) Received: from smtpin10.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay05.hostedemail.com (Postfix) with ESMTP id F0F95181AEF0B for ; Wed, 16 Jun 2021 16:00:57 +0000 (UTC) X-FDA: 78260050554.10.135BA83 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by imf14.hostedemail.com (Postfix) with ESMTP id 0D589C0633D6 for ; Wed, 16 Jun 2021 16:00:46 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 4233661159; Wed, 16 Jun 2021 16:00:54 +0000 (UTC) Date: Wed, 16 Jun 2021 17:00:51 +0100 From: Catalin Marinas To: "Russell King (Oracle)" Cc: Peter Zijlstra , Andy Lutomirski , x86@kernel.org, Dave Hansen , LKML , linux-mm@kvack.org, Andrew Morton , Mathieu Desnoyers , Nicholas Piggin , linux-arm-kernel@lists.infradead.org, Will Deacon Subject: Re: [PATCH 7/8] membarrier: Remove arm (32) support for SYNC_CORE Message-ID: <20210616160050.GE22433@arm.com> References: <2142129092ff9aa00e600c42a26c4015b7f5ceec.1623813516.git.luto@kernel.org> <20210616103446.GC22278@shell.armlinux.org.uk> <20210616132226.GD22278@shell.armlinux.org.uk> <20210616150456.GC22433@arm.com> <20210616152326.GG22278@shell.armlinux.org.uk> <20210616154529.GD22433@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210616154529.GD22433@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Authentication-Results: imf14.hostedemail.com; dkim=none; dmarc=fail reason="SPF not aligned (relaxed), No valid DKIM" header.from=arm.com (policy=none); spf=pass (imf14.hostedemail.com: domain of cmarinas@kernel.org designates 198.145.29.99 as permitted sender) smtp.mailfrom=cmarinas@kernel.org X-Rspamd-Server: rspam02 X-Stat-Signature: w1fh448yu7e3jwawmzmi7yrbtb6nq31e X-Rspamd-Queue-Id: 0D589C0633D6 X-HE-Tag: 1623859246-132670 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Jun 16, 2021 at 04:45:29PM +0100, Catalin Marinas wrote: > On Wed, Jun 16, 2021 at 04:23:26PM +0100, Russell King wrote: > > On Wed, Jun 16, 2021 at 04:04:56PM +0100, Catalin Marinas wrote: > > > The simpler fix for flush_icache_range() is to disable preemption, read > > > a word in a cacheline to force any dirty lines on another CPU to be > > > evicted and then issue the D-cache maintenance (for those cache lines > > > which are still dirty on the current CPU). > > > > Is just reading sufficient? If so, why do we do a read-then-write in > > the MPCore DMA cache ops? Don't we need the write to force exclusive > > ownership? If we don't have exclusive ownership of the dirty line, > > how can we be sure to write it out of the caches? > > For cleaning (which is the case for I/D coherency), we only need reading > since we are fine with clean lines being left in the D-cache on other > CPUs. For invalidation, we indeed need to force the exclusive ownership, > hence the write. Ah, I'm not sure the I-cache is broadcast in hardware on ARM11MPCore either. So fixing the D side won't be sufficient. -- Catalin