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Wed, 16 Jun 2021 17:27:16 +0100 Date: Wed, 16 Jun 2021 17:27:16 +0100 From: "Russell King (Oracle)" To: Catalin Marinas , Linus Walleij , Krzysztof Halasa , Neil Armstrong Cc: Peter Zijlstra , Andy Lutomirski , x86@kernel.org, Dave Hansen , LKML , linux-mm@kvack.org, Andrew Morton , Mathieu Desnoyers , Nicholas Piggin , linux-arm-kernel@lists.infradead.org, Will Deacon Subject: Re: [PATCH 7/8] membarrier: Remove arm (32) support for SYNC_CORE Message-ID: <20210616162716.GH22278@shell.armlinux.org.uk> References: <2142129092ff9aa00e600c42a26c4015b7f5ceec.1623813516.git.luto@kernel.org> <20210616103446.GC22278@shell.armlinux.org.uk> <20210616132226.GD22278@shell.armlinux.org.uk> <20210616150456.GC22433@arm.com> <20210616152326.GG22278@shell.armlinux.org.uk> <20210616154529.GD22433@arm.com> <20210616160050.GE22433@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210616160050.GE22433@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 56A02E000255 X-Stat-Signature: 37ue187yik1w1qi1xrsw1ztai36j3uke Authentication-Results: imf21.hostedemail.com; dkim=pass header.d=armlinux.org.uk header.s=pandora-2019 header.b=N0MaDPZZ; dmarc=pass (policy=none) header.from=armlinux.org.uk; spf=none (imf21.hostedemail.com: domain of linux@armlinux.org.uk has no SPF policy when checking 78.32.30.218) smtp.mailfrom=linux@armlinux.org.uk X-HE-Tag: 1623860841-367278 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Jun 16, 2021 at 05:00:51PM +0100, Catalin Marinas wrote: > On Wed, Jun 16, 2021 at 04:45:29PM +0100, Catalin Marinas wrote: > > On Wed, Jun 16, 2021 at 04:23:26PM +0100, Russell King wrote: > > > On Wed, Jun 16, 2021 at 04:04:56PM +0100, Catalin Marinas wrote: > > > > The simpler fix for flush_icache_range() is to disable preemption, read > > > > a word in a cacheline to force any dirty lines on another CPU to be > > > > evicted and then issue the D-cache maintenance (for those cache lines > > > > which are still dirty on the current CPU). > > > > > > Is just reading sufficient? If so, why do we do a read-then-write in > > > the MPCore DMA cache ops? Don't we need the write to force exclusive > > > ownership? If we don't have exclusive ownership of the dirty line, > > > how can we be sure to write it out of the caches? > > > > For cleaning (which is the case for I/D coherency), we only need reading > > since we are fine with clean lines being left in the D-cache on other > > CPUs. For invalidation, we indeed need to force the exclusive ownership, > > hence the write. > > Ah, I'm not sure the I-cache is broadcast in hardware on ARM11MPCore > either. So fixing the D side won't be sufficient. The other question is... do we bother to fix this. Arnd tells me that the current remaining ARM11MPCore users are: - CNS3xxx (where there is some martinal interest in the Gateworks Laguna platform) - Similar for OXNAS - There used to be the Realview MPCore tile - I haven't turned that on in ages, and it may be that the 3V cell that backs up the encryption keys is dead so it may not even boot. - Not sure about the story with QEMU - Arnd doesn't think there would be a problem there as it may not model caches. So it seems to come down to a question about CNS3xxx and OXNAS. If these aren't being used, maybe we can drop ARM11MPCore support and the associated platforms? Linus, Krzysztof, Neil, any input? Thanks. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!