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Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Andrey Ryabinin , Alexander Potapenko , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [RFCv2 00/10] Linear Address Masking enabling Date: Wed, 11 May 2022 05:27:40 +0300 Message-Id: <20220511022751.65540-1-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 9CF15A0092 X-Stat-Signature: 8c4cgeom9jn3wshhoos8xar5u5o7f9eo Authentication-Results: imf15.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=fhjDZ4oS; dmarc=pass (policy=none) header.from=intel.com; spf=none (imf15.hostedemail.com: domain of kirill.shutemov@linux.intel.com has no SPF policy when checking 134.134.136.100) smtp.mailfrom=kirill.shutemov@linux.intel.com X-Rspam-User: X-HE-Tag: 1652236168-163413 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi all. Here's long overdue update on LAM enabling. # Description # Linear Address Masking[1] (LAM) modifies the checking that is applied to 64-bit linear addresses, allowing software to use of the untranslated address bits for metadata. The patchset brings support for LAM for userspace addresses. The most sensitive part of enabling is change in tlb.c, where CR3 flags get set. Please take a look that what I'm doing makes sense. The feature competes for bits with 5-level paging: LAM_U48 makes it impossible to map anything about 47-bits. The patchset made these capability mutually exclusive: whatever used first wins. LAM_U57 can be combined with mappings above 47-bits. [1] ISE, Chapter 14. https://software.intel.com/content/dam/develop/external/us/en/documents-tps/architecture-instruction-set-extensions-programming-reference.pdf # What's new # The main change is interface rework. It is now arch_prctl(2)-based and suppose to be extendable to CET. QEMU implementation is also updated. It can now be applied onto current master branch. QEMU patch as it is was rejected by upstream, but it is functinal and can be used for testing. Please take a look. Any suggestions are welcome. v2: - Rebased onto v5.18-rc1 - New arch_prctl(2)-based API - Expose status of LAM (or other thread features) in /proc/$PID/arch_status. Kirill A. Shutemov (10): x86/mm: Fix CR3_ADDR_MASK x86: CPUID and CR3/CR4 flags for Linear Address Masking x86: Introduce userspace API to handle per-thread features x86/mm: Introduce X86_THREAD_LAM_U48 and X86_THREAD_LAM_U57 x86/mm: Provide untagged_addr() helper x86/uaccess: Remove tags from the address before checking x86/mm: Handle tagged memory accesses from kernel threads x86/mm: Make LAM_U48 and mappings above 47-bits mutually exclusive x86/mm: Add userspace API to enable Linear Address Masking x86: Expose thread features status in /proc/$PID/arch_status arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/elf.h | 3 +- arch/x86/include/asm/mmu.h | 1 + arch/x86/include/asm/mmu_context.h | 13 +++ arch/x86/include/asm/page_32.h | 3 + arch/x86/include/asm/page_64.h | 20 ++++ arch/x86/include/asm/processor-flags.h | 2 +- arch/x86/include/asm/processor.h | 3 + arch/x86/include/asm/tlbflush.h | 5 + arch/x86/include/asm/uaccess.h | 15 ++- arch/x86/include/uapi/asm/prctl.h | 8 ++ arch/x86/include/uapi/asm/processor-flags.h | 6 + arch/x86/kernel/Makefile | 2 + arch/x86/kernel/fpu/xstate.c | 47 -------- arch/x86/kernel/proc.c | 63 ++++++++++ arch/x86/kernel/process.c | 56 +++++++++ arch/x86/kernel/process.h | 2 + arch/x86/kernel/process_64.c | 46 ++++++++ arch/x86/kernel/sys_x86_64.c | 5 +- arch/x86/mm/hugetlbpage.c | 6 +- arch/x86/mm/mmap.c | 9 +- arch/x86/mm/tlb.c | 123 +++++++++++++++++--- 22 files changed, 367 insertions(+), 72 deletions(-) create mode 100644 arch/x86/kernel/proc.c -- 2.35.1