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arm64-buildonly-randconfig-r001-20220721 (https://download.01.org/0day-ci/archive/20220722/202207221521.faQAiLHe-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=651ff8d8cedf95e992cbb4147dbc96965fd2e948 git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git git fetch --no-tags linux-next master git checkout 651ff8d8cedf95e992cbb4147dbc96965fd2e948 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash arch/arm64/ If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot All errors (new ones prefixed by >>): arch/arm64/kernel/head.S: Assembler messages: >> arch/arm64/kernel/head.S:334: Error: immediate cannot be moved by a single instruction arch/arm64/kernel/head.S:343: Error: immediate cannot be moved by a single instruction arch/arm64/kernel/head.S:354: Error: immediate cannot be moved by a single instruction arch/arm64/kernel/head.S:379: Error: immediate cannot be moved by a single instruction vim +334 arch/arm64/kernel/head.S fa2a8445b1d3810 Kristina Martsenko 2017-12-13 312 fa2a8445b1d3810 Kristina Martsenko 2017-12-13 313 /* fa2a8445b1d3810 Kristina Martsenko 2017-12-13 314 * If VA_BITS < 48, we have to configure an additional table level. fa2a8445b1d3810 Kristina Martsenko 2017-12-13 315 * First, we have to verify our assumption that the current value of fa2a8445b1d3810 Kristina Martsenko 2017-12-13 316 * VA_BITS was chosen such that all translation levels are fully fa2a8445b1d3810 Kristina Martsenko 2017-12-13 317 * utilised, and that lowering T0SZ will always result in an additional fa2a8445b1d3810 Kristina Martsenko 2017-12-13 318 * translation level to be configured. fa2a8445b1d3810 Kristina Martsenko 2017-12-13 319 */ fa2a8445b1d3810 Kristina Martsenko 2017-12-13 320 #if VA_BITS != EXTRA_SHIFT fa2a8445b1d3810 Kristina Martsenko 2017-12-13 321 #error "Mismatch between VA_BITS and page size/number of translation levels" dd006da21646f1c Ard Biesheuvel 2015-03-19 322 #endif fa2a8445b1d3810 Kristina Martsenko 2017-12-13 323 #else 53519ddf5894476 Ard Biesheuvel 2022-06-24 324 #define IDMAP_PGD_ORDER (PHYS_MASK_SHIFT - PGDIR_SHIFT) 50fcd39d24c24bb Ard Biesheuvel 2022-06-24 325 #define EXTRA_SHIFT fa2a8445b1d3810 Kristina Martsenko 2017-12-13 326 /* fa2a8445b1d3810 Kristina Martsenko 2017-12-13 327 * If VA_BITS == 48, we don't have to configure an additional fa2a8445b1d3810 Kristina Martsenko 2017-12-13 328 * translation level, but the top-level table has more entries. fa2a8445b1d3810 Kristina Martsenko 2017-12-13 329 */ fa2a8445b1d3810 Kristina Martsenko 2017-12-13 330 #endif c3cee924bd85518 Ard Biesheuvel 2022-06-24 331 adrp x0, init_idmap_pg_dir c3cee924bd85518 Ard Biesheuvel 2022-06-24 332 adrp x3, _text f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 333 adrp x6, _end + MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE c3cee924bd85518 Ard Biesheuvel 2022-06-24 @334 mov x7, SWAPPER_RX_MMUFLAGS 0370b31e48454d8 Steve Capper 2018-01-11 335 50fcd39d24c24bb Ard Biesheuvel 2022-06-24 336 map_memory x0, x1, x3, x6, x7, x3, IDMAP_PGD_ORDER, x10, x11, x12, x13, x14, EXTRA_SHIFT 034edabe6cf1d0d Laura Abbott 2014-11-21 337 c3cee924bd85518 Ard Biesheuvel 2022-06-24 338 /* Remap the kernel page tables r/w in the ID map */ c3cee924bd85518 Ard Biesheuvel 2022-06-24 339 adrp x1, _text c3cee924bd85518 Ard Biesheuvel 2022-06-24 340 adrp x2, init_pg_dir c3cee924bd85518 Ard Biesheuvel 2022-06-24 341 adrp x3, init_pg_end c3cee924bd85518 Ard Biesheuvel 2022-06-24 342 bic x4, x2, #SWAPPER_BLOCK_SIZE - 1 c3cee924bd85518 Ard Biesheuvel 2022-06-24 343 mov x5, SWAPPER_RW_MMUFLAGS c3cee924bd85518 Ard Biesheuvel 2022-06-24 344 mov x6, #SWAPPER_BLOCK_SHIFT c3cee924bd85518 Ard Biesheuvel 2022-06-24 345 bl remap_region c3cee924bd85518 Ard Biesheuvel 2022-06-24 346 f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 347 /* Remap the FDT after the kernel image */ f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 348 adrp x1, _text f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 349 adrp x22, _end + SWAPPER_BLOCK_SIZE f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 350 bic x2, x22, #SWAPPER_BLOCK_SIZE - 1 f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 351 bfi x22, x21, #0, #SWAPPER_BLOCK_SHIFT // remapped FDT address f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 352 add x3, x2, #MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 353 bic x4, x21, #SWAPPER_BLOCK_SIZE - 1 f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 354 mov x5, SWAPPER_RW_MMUFLAGS f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 355 mov x6, #SWAPPER_BLOCK_SHIFT f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 356 bl remap_region f70b3a23324a2d3 Ard Biesheuvel 2022-06-24 357 034edabe6cf1d0d Laura Abbott 2014-11-21 358 /* e42ade29e3bcb32 Ard Biesheuvel 2022-06-24 359 * Since the page tables have been populated with non-cacheable e42ade29e3bcb32 Ard Biesheuvel 2022-06-24 360 * accesses (MMU disabled), invalidate those tables again to e42ade29e3bcb32 Ard Biesheuvel 2022-06-24 361 * remove any speculatively loaded cache lines. 034edabe6cf1d0d Laura Abbott 2014-11-21 362 */ e42ade29e3bcb32 Ard Biesheuvel 2022-06-24 363 dmb sy e42ade29e3bcb32 Ard Biesheuvel 2022-06-24 364 c3cee924bd85518 Ard Biesheuvel 2022-06-24 365 adrp x0, init_idmap_pg_dir c3cee924bd85518 Ard Biesheuvel 2022-06-24 366 adrp x1, init_idmap_pg_end c3cee924bd85518 Ard Biesheuvel 2022-06-24 367 bl dcache_inval_poc c3cee924bd85518 Ard Biesheuvel 2022-06-24 368 ret x28 e42ade29e3bcb32 Ard Biesheuvel 2022-06-24 369 SYM_FUNC_END(create_idmap) e42ade29e3bcb32 Ard Biesheuvel 2022-06-24 370 :::::: The code at line 334 was first introduced by commit :::::: c3cee924bd855184d15bc4aa6088dcf8e2c1394c arm64: head: cover entire kernel image in initial ID map :::::: TO: Ard Biesheuvel :::::: CC: Will Deacon -- 0-DAY CI Kernel Test Service https://01.org/lkp