From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1FE4C433F5 for ; Mon, 10 Oct 2022 21:21:10 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 3B3B68E0001; Mon, 10 Oct 2022 17:21:10 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 3631F6B0073; Mon, 10 Oct 2022 17:21:10 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 2043C8E0001; Mon, 10 Oct 2022 17:21:10 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id 001046B0071 for ; Mon, 10 Oct 2022 17:21:09 -0400 (EDT) Received: from smtpin29.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay05.hostedemail.com (Postfix) with ESMTP id 9AD6940E73 for ; Mon, 10 Oct 2022 21:21:09 +0000 (UTC) X-FDA: 80006310258.29.88AB151 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by imf05.hostedemail.com (Postfix) with ESMTP id C0D08100029 for ; Mon, 10 Oct 2022 21:21:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665436866; x=1696972866; h=date:from:to:cc:subject:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6bewUPV0oMJXxMHM3wLoUnCgf8IY9mzn6Zi1LNI1H9M=; b=Q4jzQxoR/N4ZgIFWCp7XUxdG8aAZP2uH2ixtJTnLoYO/311u0MwzodQk hOEfaO7xkT1C25U6TONg8XlvwNryqJBCgUK/XuldnMxs070Wpn6j1gzen obIZjFt2C0p7f5FYZLfzyvpdiUCgvKGi/MnLuPgiK7MQciP4LqYlAlPDd jYufOgrbkIghejitRhjKgLhxWtFyCAZIOvYhfomfWGIAC9HuVkly/Ciro /hplIjEZINlgGJ9xGPmQDPQoTgJPA6iIi2A7KR9N8zPlrXmYHbUaRYU3r jw8Y9LNjudSUxu1Iwe3Pb9FfgwUB5LevNDmqGH0AnZvbcq14q7wBwhRwT g==; X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="301948505" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="301948505" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2022 14:21:05 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="626116004" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="626116004" Received: from jacob-builder.jf.intel.com (HELO jacob-builder) ([10.7.198.157]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2022 14:21:05 -0700 Date: Mon, 10 Oct 2022 14:24:28 -0700 From: Jacob Pan To: "Kirill A. Shutemov" Cc: Dave Hansen , Andy Lutomirski , Peter Zijlstra , x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, jacob.jun.pan@linux.intel.com, "Lu, Baolu" Subject: Re: [PATCHv9 10/14] x86/mm, iommu/sva: Make LAM and SVM mutually exclusive Message-ID: <20221010142428.6f8bfc05@jacob-builder> In-Reply-To: <20220930144758.30232-11-kirill.shutemov@linux.intel.com> References: <20220930144758.30232-1-kirill.shutemov@linux.intel.com> <20220930144758.30232-11-kirill.shutemov@linux.intel.com> Organization: OTC X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1665436867; a=rsa-sha256; cv=none; b=vcARz2nIQKieEf5gtLiiiNhbFCMy3KvimlqO9PtIYdNAqZ+0HD5aq4ayAG1zQ2PLk55gFA 1rfLI+POtg9yv9ERXNKyw6Yy4S95wPDjlRTQvuI20bzX4lHNhvvpd/6sDa93kIUMt6Tf8C jRXP/VgQPwuHyu7S9B3945iuPte3lqY= ARC-Authentication-Results: i=1; imf05.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=Q4jzQxoR; dmarc=fail reason="No valid SPF" header.from=intel.com (policy=none); spf=none (imf05.hostedemail.com: domain of jacob.jun.pan@linux.intel.com has no SPF policy when checking 192.55.52.93) smtp.mailfrom=jacob.jun.pan@linux.intel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1665436867; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=Za9Pl/sai708bOb12NzokuDHx7oeHbzPIi/XgIouw1s=; b=bH3KguCA0omYzg9700+/wDEhwtn3nHGsRGZV2QWElk1s5vi5QQ+6n/HkjCmB6LREpCp505 8KuDNN9pQVkgmcUhvxDqQgbGaIqS6q+tnQnjncUSwQZOFjsMU8RtpsjuhsBgWpQS0K85yS qkZ7cTHv0rDF/TriFoHsQfKk9031uvg= X-Stat-Signature: huwtmsg4a6scnt74ruhshesqi9ow5n3i X-Rspamd-Queue-Id: C0D08100029 Authentication-Results: imf05.hostedemail.com; dkim=none ("invalid DKIM record") header.d=intel.com header.s=Intel header.b=Q4jzQxoR; dmarc=fail reason="No valid SPF" header.from=intel.com (policy=none); spf=none (imf05.hostedemail.com: domain of jacob.jun.pan@linux.intel.com has no SPF policy when checking 192.55.52.93) smtp.mailfrom=jacob.jun.pan@linux.intel.com X-Rspam-User: X-Rspamd-Server: rspam03 X-HE-Tag: 1665436866-209187 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi Kirill, On Fri, 30 Sep 2022 17:47:54 +0300, "Kirill A. Shutemov" wrote: > IOMMU and SVM-capable devices know nothing about LAM and only expect > canonical addresses. Attempt to pass down tagged pointer will lead to > address translation failure. > > By default do not allow to enable both LAM and use SVM in the same > process. > > The new ARCH_FORCE_TAGGED_SVM arch_prctl() overrides the limitation. > By using the arch_prctl() userspace takes responsibility to never pass > tagged address to the device. > > Signed-off-by: Kirill A. Shutemov Reviewed-by: Jacob Pan +Baolu who is doing SVA lib refactoring, perhaps cc as well. > --- > arch/x86/include/asm/mmu.h | 6 ++++-- > arch/x86/include/asm/mmu_context.h | 2 ++ > arch/x86/include/uapi/asm/prctl.h | 1 + > arch/x86/kernel/process_64.c | 13 +++++++++++++ > drivers/iommu/iommu-sva-lib.c | 12 ++++++++++++ > include/linux/mmu_context.h | 4 ++++ > 6 files changed, 36 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h > index 2fdb390040b5..cce9b32b0d6d 100644 > --- a/arch/x86/include/asm/mmu.h > +++ b/arch/x86/include/asm/mmu.h > @@ -9,9 +9,11 @@ > #include > > /* Uprobes on this MM assume 32-bit code */ > -#define MM_CONTEXT_UPROBE_IA32 BIT(0) > +#define MM_CONTEXT_UPROBE_IA32 BIT(0) > /* vsyscall page is accessible on this MM */ > -#define MM_CONTEXT_HAS_VSYSCALL BIT(1) > +#define MM_CONTEXT_HAS_VSYSCALL BIT(1) > +/* Allow LAM and SVM coexisting */ > +#define MM_CONTEXT_FORCE_TAGGED_SVM BIT(2) > > /* > * x86 has arch-specific MMU state beyond what lives in mm_struct. > diff --git a/arch/x86/include/asm/mmu_context.h > b/arch/x86/include/asm/mmu_context.h index b0e9ea23758b..6b9ac2c60cec > 100644 --- a/arch/x86/include/asm/mmu_context.h > +++ b/arch/x86/include/asm/mmu_context.h > @@ -113,6 +113,8 @@ static inline void mm_reset_untag_mask(struct > mm_struct *mm) mm->context.untag_mask = -1UL; > } > > +#define arch_pgtable_dma_compat(mm) \ > + (!mm_lam_cr3_mask(mm) || (mm->context.flags & > MM_CONTEXT_FORCE_TAGGED_SVM)) #else > > static inline unsigned long mm_lam_cr3_mask(struct mm_struct *mm) > diff --git a/arch/x86/include/uapi/asm/prctl.h > b/arch/x86/include/uapi/asm/prctl.h index a31e27b95b19..7bd22defb558 > 100644 --- a/arch/x86/include/uapi/asm/prctl.h > +++ b/arch/x86/include/uapi/asm/prctl.h > @@ -23,5 +23,6 @@ > #define ARCH_GET_UNTAG_MASK 0x4001 > #define ARCH_ENABLE_TAGGED_ADDR 0x4002 > #define ARCH_GET_MAX_TAG_BITS 0x4003 > +#define ARCH_FORCE_TAGGED_SVM 0x4004 > > #endif /* _ASM_X86_PRCTL_H */ > diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c > index 1730c2fcc7ab..d7ec5c7f49a7 100644 > --- a/arch/x86/kernel/process_64.c > +++ b/arch/x86/kernel/process_64.c > @@ -782,6 +782,13 @@ static int prctl_enable_tagged_addr(struct mm_struct > *mm, unsigned long nr_bits) goto out; > } > > +#ifdef CONFIG_IOMMU_SVA > + if (pasid_valid(mm->pasid) && > + !(mm->context.flags & MM_CONTEXT_FORCE_TAGGED_SVM)) { > + ret = -EBUSY; > + goto out; > + } > +#endif > if (!nr_bits) { > ret = -EINVAL; > goto out; > @@ -892,6 +899,12 @@ long do_arch_prctl_64(struct task_struct *task, int > option, unsigned long arg2) (unsigned long __user *)arg2); > case ARCH_ENABLE_TAGGED_ADDR: > return prctl_enable_tagged_addr(task->mm, arg2); > + case ARCH_FORCE_TAGGED_SVM: > + if (mmap_write_lock_killable(task->mm)) > + return -EINTR; > + task->mm->context.flags |= MM_CONTEXT_FORCE_TAGGED_SVM; > + mmap_write_unlock(task->mm); > + return 0; > case ARCH_GET_MAX_TAG_BITS: > if (!cpu_feature_enabled(X86_FEATURE_LAM)) > return put_user(0, (unsigned long __user *)arg2); > diff --git a/drivers/iommu/iommu-sva-lib.c b/drivers/iommu/iommu-sva-lib.c > index 106506143896..593ae2472e2c 100644 > --- a/drivers/iommu/iommu-sva-lib.c > +++ b/drivers/iommu/iommu-sva-lib.c > @@ -2,6 +2,8 @@ > /* > * Helpers for IOMMU drivers implementing SVA > */ > +#include > +#include > #include > #include > > @@ -31,6 +33,15 @@ int iommu_sva_alloc_pasid(struct mm_struct *mm, > ioasid_t min, ioasid_t max) min == 0 || max < min) > return -EINVAL; > > + /* Serialize against address tagging enabling */ > + if (mmap_write_lock_killable(mm)) > + return -EINTR; > + > + if (!arch_pgtable_dma_compat(mm)) { > + mmap_write_unlock(mm); > + return -EBUSY; > + } > + > mutex_lock(&iommu_sva_lock); > /* Is a PASID already associated with this mm? */ > if (pasid_valid(mm->pasid)) { > @@ -46,6 +57,7 @@ int iommu_sva_alloc_pasid(struct mm_struct *mm, > ioasid_t min, ioasid_t max) mm_pasid_set(mm, pasid); > out: > mutex_unlock(&iommu_sva_lock); > + mmap_write_unlock(mm); > return ret; > } > EXPORT_SYMBOL_GPL(iommu_sva_alloc_pasid); > diff --git a/include/linux/mmu_context.h b/include/linux/mmu_context.h > index b9b970f7ab45..115e2b518079 100644 > --- a/include/linux/mmu_context.h > +++ b/include/linux/mmu_context.h > @@ -28,4 +28,8 @@ static inline void leave_mm(int cpu) { } > # define task_cpu_possible(cpu, p) cpumask_test_cpu((cpu), > task_cpu_possible_mask(p)) #endif > > +#ifndef arch_pgtable_dma_compat > +#define arch_pgtable_dma_compat(mm) true > +#endif > + > #endif Thanks, Jacob