* Re: [PATCH v8 4/6] RISC-V: Detect unaligned vector accesses supported
[not found] <20240819212605.1837175-5-jesse@rivosinc.com>
@ 2024-08-20 8:02 ` kernel test robot
2024-08-20 9:25 ` kernel test robot
1 sibling, 0 replies; 2+ messages in thread
From: kernel test robot @ 2024-08-20 8:02 UTC (permalink / raw)
To: Jesse Taube, linux-riscv
Cc: oe-kbuild-all, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Clément Léger, Evan Green, Andrew Jones, Jesse Taube,
Charlie Jenkins, Xiao Wang, Andy Chiu, Eric Biggers, Greentime Hu,
Björn Töpel, Heiko Stuebner, Costa Shulyupin,
Andrew Morton, Linux Memory Management List, Baoquan He,
Anup Patel, Zong Li, Sami Tolvanen, Ben Dooks, Alexandre Ghiti,
Gustavo A. R. Silva, Erick Archer
Hi Jesse,
kernel test robot noticed the following build errors:
[auto build test ERROR on 32d5f7add080a936e28ab4142bfeea6b06999789]
url: https://github.com/intel-lab-lkp/linux/commits/Jesse-Taube/RISC-V-Check-scalar-unaligned-access-on-all-CPUs/20240820-052900
base: 32d5f7add080a936e28ab4142bfeea6b06999789
patch link: https://lore.kernel.org/r/20240819212605.1837175-5-jesse%40rivosinc.com
patch subject: [PATCH v8 4/6] RISC-V: Detect unaligned vector accesses supported
config: riscv-allnoconfig (https://download.01.org/0day-ci/archive/20240820/202408201543.4MIUQPd7-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 14.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240820/202408201543.4MIUQPd7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408201543.4MIUQPd7-lkp@intel.com/
All errors (new ones prefixed by >>):
arch/riscv/kernel/sys_hwprobe.c: In function 'hwprobe_one_pair':
>> arch/riscv/kernel/sys_hwprobe.c:263:14: error: 'RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF' undeclared (first use in this function)
263 | case RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF:
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/riscv/kernel/sys_hwprobe.c:263:14: note: each undeclared identifier is reported only once for each function it appears in
vim +/RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF +263 arch/riscv/kernel/sys_hwprobe.c
234
235 static void hwprobe_one_pair(struct riscv_hwprobe *pair,
236 const struct cpumask *cpus)
237 {
238 switch (pair->key) {
239 case RISCV_HWPROBE_KEY_MVENDORID:
240 case RISCV_HWPROBE_KEY_MARCHID:
241 case RISCV_HWPROBE_KEY_MIMPID:
242 hwprobe_arch_id(pair, cpus);
243 break;
244 /*
245 * The kernel already assumes that the base single-letter ISA
246 * extensions are supported on all harts, and only supports the
247 * IMA base, so just cheat a bit here and tell that to
248 * userspace.
249 */
250 case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
251 pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
252 break;
253
254 case RISCV_HWPROBE_KEY_IMA_EXT_0:
255 hwprobe_isa_ext0(pair, cpus);
256 break;
257
258 case RISCV_HWPROBE_KEY_CPUPERF_0:
259 case RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF:
260 pair->value = hwprobe_misaligned(cpus);
261 break;
262
> 263 case RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF:
264 pair->value = hwprobe_vec_misaligned(cpus);
265 break;
266
267 case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
268 pair->value = 0;
269 if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
270 pair->value = riscv_cboz_block_size;
271 break;
272 case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
273 pair->value = user_max_virt_addr();
274 break;
275
276 case RISCV_HWPROBE_KEY_TIME_CSR_FREQ:
277 pair->value = riscv_timebase;
278 break;
279
280 /*
281 * For forward compatibility, unknown keys don't fail the whole
282 * call, but get their element key set to -1 and value set to 0
283 * indicating they're unrecognized.
284 */
285 default:
286 pair->key = -1;
287 pair->value = 0;
288 break;
289 }
290 }
291
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH v8 4/6] RISC-V: Detect unaligned vector accesses supported
[not found] <20240819212605.1837175-5-jesse@rivosinc.com>
2024-08-20 8:02 ` [PATCH v8 4/6] RISC-V: Detect unaligned vector accesses supported kernel test robot
@ 2024-08-20 9:25 ` kernel test robot
1 sibling, 0 replies; 2+ messages in thread
From: kernel test robot @ 2024-08-20 9:25 UTC (permalink / raw)
To: Jesse Taube, linux-riscv
Cc: llvm, oe-kbuild-all, Jonathan Corbet, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Clément Léger, Evan Green,
Andrew Jones, Jesse Taube, Charlie Jenkins, Xiao Wang, Andy Chiu,
Eric Biggers, Greentime Hu, Björn Töpel, Heiko Stuebner,
Costa Shulyupin, Andrew Morton, Linux Memory Management List,
Baoquan He, Anup Patel, Zong Li, Sami Tolvanen, Ben Dooks,
Alexandre Ghiti, Gustavo A. R. Silva, Erick Archer
Hi Jesse,
kernel test robot noticed the following build errors:
[auto build test ERROR on 32d5f7add080a936e28ab4142bfeea6b06999789]
url: https://github.com/intel-lab-lkp/linux/commits/Jesse-Taube/RISC-V-Check-scalar-unaligned-access-on-all-CPUs/20240820-052900
base: 32d5f7add080a936e28ab4142bfeea6b06999789
patch link: https://lore.kernel.org/r/20240819212605.1837175-5-jesse%40rivosinc.com
patch subject: [PATCH v8 4/6] RISC-V: Detect unaligned vector accesses supported
config: riscv-defconfig (https://download.01.org/0day-ci/archive/20240820/202408201720.u8SfprDk-lkp@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project 26670e7fa4f032a019d23d56c6a02926e854e8af)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240820/202408201720.u8SfprDk-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408201720.u8SfprDk-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from arch/riscv/kernel/sys_hwprobe.c:7:
In file included from include/linux/syscalls.h:93:
In file included from include/trace/syscall.h:7:
In file included from include/linux/trace_events.h:6:
In file included from include/linux/ring_buffer.h:5:
In file included from include/linux/mm.h:2228:
include/linux/vmstat.h:514:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
514 | return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
| ~~~~~~~~~~~ ^ ~~~
>> arch/riscv/kernel/sys_hwprobe.c:263:7: error: use of undeclared identifier 'RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF'
263 | case RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF:
| ^
1 warning and 1 error generated.
vim +/RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF +263 arch/riscv/kernel/sys_hwprobe.c
234
235 static void hwprobe_one_pair(struct riscv_hwprobe *pair,
236 const struct cpumask *cpus)
237 {
238 switch (pair->key) {
239 case RISCV_HWPROBE_KEY_MVENDORID:
240 case RISCV_HWPROBE_KEY_MARCHID:
241 case RISCV_HWPROBE_KEY_MIMPID:
242 hwprobe_arch_id(pair, cpus);
243 break;
244 /*
245 * The kernel already assumes that the base single-letter ISA
246 * extensions are supported on all harts, and only supports the
247 * IMA base, so just cheat a bit here and tell that to
248 * userspace.
249 */
250 case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
251 pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
252 break;
253
254 case RISCV_HWPROBE_KEY_IMA_EXT_0:
255 hwprobe_isa_ext0(pair, cpus);
256 break;
257
258 case RISCV_HWPROBE_KEY_CPUPERF_0:
259 case RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF:
260 pair->value = hwprobe_misaligned(cpus);
261 break;
262
> 263 case RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF:
264 pair->value = hwprobe_vec_misaligned(cpus);
265 break;
266
267 case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
268 pair->value = 0;
269 if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
270 pair->value = riscv_cboz_block_size;
271 break;
272 case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
273 pair->value = user_max_virt_addr();
274 break;
275
276 case RISCV_HWPROBE_KEY_TIME_CSR_FREQ:
277 pair->value = riscv_timebase;
278 break;
279
280 /*
281 * For forward compatibility, unknown keys don't fail the whole
282 * call, but get their element key set to -1 and value set to 0
283 * indicating they're unrecognized.
284 */
285 default:
286 pair->key = -1;
287 pair->value = 0;
288 break;
289 }
290 }
291
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 2+ messages in thread
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[not found] <20240819212605.1837175-5-jesse@rivosinc.com>
2024-08-20 8:02 ` [PATCH v8 4/6] RISC-V: Detect unaligned vector accesses supported kernel test robot
2024-08-20 9:25 ` kernel test robot
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