From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DDF2C021B2 for ; Mon, 24 Feb 2025 02:02:59 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 840236B007B; Sun, 23 Feb 2025 21:02:58 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 7F0486B0083; Sun, 23 Feb 2025 21:02:58 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 6B7B16B0085; Sun, 23 Feb 2025 21:02:58 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id 4EB6A6B007B for ; Sun, 23 Feb 2025 21:02:58 -0500 (EST) Received: from smtpin19.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay07.hostedemail.com (Postfix) with ESMTP id EAD1E1606BC for ; Mon, 24 Feb 2025 02:02:57 +0000 (UTC) X-FDA: 83153189994.19.8D8C537 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf26.hostedemail.com (Postfix) with ESMTP id 4F4F4140004 for ; Mon, 24 Feb 2025 02:02:56 +0000 (UTC) Authentication-Results: imf26.hostedemail.com; dkim=none; spf=pass (imf26.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1740362576; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aMhxT52ew/xcfgdNOcKZU6VIAsNTrA7JCfmaYDK1zLo=; b=75JQBR0hHKvpfmT5H3YUcX7aBV4sDnKJU+0tExioLXBYkNaPiaXvbxtz5c/wo6zegWHljN 5barsey4Cwnvgu8cgRQYE1zZRFjmKchkxot9loGogReo/ousAEVzQAV1RqXaE8bB4mnAmi MiiLW7Ds2KYvqrODN3lw18j/ZhrQXnQ= ARC-Authentication-Results: i=1; imf26.hostedemail.com; dkim=none; spf=pass (imf26.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1740362576; a=rsa-sha256; cv=none; b=YANnb3yycnMktJGN7MKew5GglOmVZjymYFrQzReVp56bQmFeupPXp5o9SOxH3ZqNJRAP46 cchP21dQ0NgRtIV/6ph3HFDbiVwvLkKE39FYBfflJwhXYBjF4q1h1baiJ9hcg31m3EAlqD LIkvI+Ba6PkYzwGnAKhzIU+o/ddJF00= Received: from [2601:18c:8180:83cc:5a47:caff:fe78:8708] (helo=fangorn) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tmNnA-00000000340-0LPO; Sun, 23 Feb 2025 21:01:56 -0500 Date: Sun, 23 Feb 2025 21:01:55 -0500 From: Rik van Riel To: kernel test robot Cc: x86@kernel.org, oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, mingo@kernel.org Subject: Re: [PATCH v13 08/14] x86/mm: global ASID context switch & TLB flush handling Message-ID: <20250223210155.3c90843f@fangorn> In-Reply-To: <202502240650.kzshiji7-lkp@intel.com> References: <20250223194943.3518952-9-riel@surriel.com> <202502240650.kzshiji7-lkp@intel.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.43; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Rspam-User: X-Rspamd-Server: rspam11 X-Rspamd-Queue-Id: 4F4F4140004 X-Stat-Signature: 8pssay3ugiyfnmtg1ucwtn5zaochq6oa X-HE-Tag: 1740362576-811755 X-HE-Meta: U2FsdGVkX1+cWznY2VCERzrveMvDl+HUWDJ9XjLIEQv1P8PNx/j1UoG94tI0ZP5yUiYE/41JS8WKh+AilxCi0MDIvrQZ8JiQCByE/sBix6wWWr2ndup81PGlwPMrUl1pZFlKcvr6Xf5Nv2MVawEA99pMEqzYJkd8xm4C/LKykVgxzsXgwLCWfjgwFKv5OFercaLWhZq2SEpdiH3gfOF/GvznCEFBRn34F4XbQCfQLHKMEMHEPXB/iS9cIfvshrLzLop8YJ92fyOgO/tzILBllXs7J94YTSCGAReyJmwtGHyh4afoLUtI50zdnY239MimrzKGBI5woKzEwxhipoRhdUYiTm/SVG4LA3kQw+cvMwRJ9K5MugMNUaRt4jeYFK5X1KnH1wQqe4AUv2QP5sNP5pkQKEqAP9drde6YPFno0yuO8Sj1GZ/hKXnt2CT2R5qNAdEqnm8ypXjhpy5k0MJBkfD6siImGSlXiA8zUkhom526Y7kOBGTN/6MtutWct7PP6FfWzM38VT42BvXPXsPQ7oCvF3PNf35Yx4vmWfwa2G9egNirYZbFrU+rFPaedNrMC8JXBmCfks6N24ctaz7wwvV58ewHTgbJwaXwswuNuEhMVuTHhsjci8OtUypaxNeyVGuKsLbUZKX6PpvuXn8mMV7qPBD1Ul1cfjtvnRW9IXiGr5Dl8InERJhJ8qyAmxytp0+9AJSalRRcLvrLgLo+BYjrl9d/rktchvVicwZqTzsE1NCvw5XbY5cpejNRt4rTfue6vpr7aTL6jfMh6qWiWP3NCgU4u5fegFnDG5jNuVYYIGGt6XBpn7RnPQ0B203IZiOt5tVXKUAv57um9TYC8hoeMqznfM+c21k98tjgTCNVT9ziIj8VKV5n0MWY2SavuEh9u3DeEpXl7yXMd+TNc4mj6tuSzN1d5TAdMErjB3GfJGwingeZKMOpgxBiCyuWrcqGQbcSGsrnYEmkbOF VP8I1x0X /H0Pk+OoyZ8bBqTAO41lbE+YQozHe/siC5AbSAjMZWVp5SUIaergSlVnC7qpp2aRk2pRWS+YJugFy0leBb01onLGpL5TE0igzmZ0nmnbO2ltURW2IqZ7iHJavmkWhnL45ohKMd8VFzu3H2SLHZ3+giUUU47VcQ2GhGBQyxkmixNQqHdi3Nzpk9Ewrn46EcttaU0uveU0mVharSvwIzOdzCmHgRfOQ8E0297I6ZhkWu2S6dqROcaoKLAFh0GeUAITV2Dd8kCVX/Wrg9YYqqAmwwudxVYZl3rVGKCDybndLUBkcEI+C6yUm1WQB4ssHENeebKiOxoG7bw/Y+QcRGSRZ2sWjpztEMi7rvs/bgVmGveCzRqxvn8jaNTowXLiv2Nk+d4Z/ock+1+FnzqAZap7VF7JRVuSMeOqc2VuJuQVZ5+ZSwjdqUSrpw063VwK3Z3AJCvlH X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Mon, 24 Feb 2025 07:08:49 +0800 kernel test robot wrote: > Hi Rik, > > kernel test robot noticed the following build errors: > > [auto build test ERROR on tip/x86/core] > [also build test ERROR on tip/x86/mm tip/master linus/master v6.14-rc4 next-20250221] This version of patch 8 fixes these compile errors. I hoped the compiler was smart enough to elide the code when broadcast TLB invalidation was disabled at the config level, but maybe that happens at a later stage in the compilation, after it's already thrown the errors... I'm not entirely happy with this, but it does seem simple enough. ---8<--- x86/mm: global ASID context switch & TLB flush handling Context switch and TLB flush support for processes that use a global ASID & PCID across all CPUs. At both context switch time and TLB flush time, we need to check whether a task is switching to a global ASID, and reload the TLB with the new ASID as appropriate. In both code paths, we also short-circuit the TLB flush if we are using a global ASID, because the global ASIDs are always kept up to date across CPUs, even while the process is not running on a CPU. Signed-off-by: Rik van Riel diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 83f1da2f1e4a..24e6531e0b1a 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -240,6 +240,11 @@ static inline bool is_dyn_asid(u16 asid) return asid < TLB_NR_DYN_ASIDS; } +static inline bool is_global_asid(u16 asid) +{ + return !is_dyn_asid(asid); +} + #ifdef CONFIG_X86_BROADCAST_TLB_FLUSH static inline u16 mm_global_asid(struct mm_struct *mm) { @@ -266,6 +271,14 @@ static inline void assign_mm_global_asid(struct mm_struct *mm, u16 asid) mm->context.asid_transition = true; smp_store_release(&mm->context.global_asid, asid); } + +static inline bool in_asid_transition(struct mm_struct *mm) +{ + if (!cpu_feature_enabled(X86_FEATURE_INVLPGB)) + return false; + + return mm && READ_ONCE(mm->context.asid_transition); +} #else static inline u16 mm_global_asid(struct mm_struct *mm) { @@ -275,6 +288,11 @@ static inline u16 mm_global_asid(struct mm_struct *mm) static inline void assign_mm_global_asid(struct mm_struct *mm, u16 asid) { } + +static inline bool in_asid_transition(struct mm_struct *mm) +{ + return false; +} #endif #ifdef CONFIG_PARAVIRT diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 405630479b90..e4aecd38ac4f 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -227,6 +227,20 @@ static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, return; } + /* + * TLB consistency for global ASIDs is maintained with hardware assisted + * remote TLB flushing. Global ASIDs are always up to date. + */ + if (static_cpu_has(X86_FEATURE_INVLPGB)) { + u16 global_asid = mm_global_asid(next); + + if (global_asid) { + *new_asid = global_asid; + *need_flush = false; + return; + } + } + if (this_cpu_read(cpu_tlbstate.invalidate_other)) clear_asid_other(); @@ -382,11 +396,30 @@ void destroy_context_free_global_asid(struct mm_struct *mm) guard(raw_spinlock_irqsave)(&global_asid_lock); +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH /* The global ASID can be re-used only after flush at wrap-around. */ __set_bit(mm->context.global_asid, global_asid_freed); mm->context.global_asid = 0; global_asid_available++; +#endif +} + +/* + * Is the mm transitioning from a CPU-local ASID to a global ASID? + */ +static bool needs_global_asid_reload(struct mm_struct *next, u16 prev_asid) +{ + u16 global_asid = mm_global_asid(next); + + if (!static_cpu_has(X86_FEATURE_INVLPGB)) + return false; + + /* Process is transitioning to a global ASID */ + if (global_asid && prev_asid != global_asid) + return true; + + return false; } /* @@ -694,7 +727,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ if (prev == next) { /* Not actually switching mm's */ - VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != + VM_WARN_ON(is_dyn_asid(prev_asid) && + this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != next->context.ctx_id); /* @@ -711,6 +745,20 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, !cpumask_test_cpu(cpu, mm_cpumask(next)))) cpumask_set_cpu(cpu, mm_cpumask(next)); + /* Check if the current mm is transitioning to a global ASID */ + if (needs_global_asid_reload(next, prev_asid)) { + next_tlb_gen = atomic64_read(&next->context.tlb_gen); + choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); + goto reload_tlb; + } + + /* + * Broadcast TLB invalidation keeps this PCID up to date + * all the time. + */ + if (is_global_asid(prev_asid)) + return; + /* * If the CPU is not in lazy TLB mode, we are just switching * from one thread in a process to another thread in the same @@ -744,6 +792,13 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ cond_mitigation(tsk); + /* + * Let nmi_uaccess_okay() and finish_asid_transition() + * know that we're changing CR3. + */ + this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING); + barrier(); + /* * Leave this CPU in prev's mm_cpumask. Atomic writes to * mm_cpumask can be expensive under contention. The CPU @@ -758,14 +813,12 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, next_tlb_gen = atomic64_read(&next->context.tlb_gen); choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); - - /* Let nmi_uaccess_okay() know that we're changing CR3. */ - this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING); - barrier(); } +reload_tlb: new_lam = mm_lam_cr3_mask(next); if (need_flush) { + VM_WARN_ON_ONCE(is_global_asid(new_asid)); this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); load_new_mm_cr3(next->pgd, new_asid, new_lam, true); @@ -884,7 +937,7 @@ static void flush_tlb_func(void *info) const struct flush_tlb_info *f = info; struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); - u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen); + u64 local_tlb_gen; bool local = smp_processor_id() == f->initiating_cpu; unsigned long nr_invalidate = 0; u64 mm_tlb_gen; @@ -907,6 +960,16 @@ static void flush_tlb_func(void *info) if (unlikely(loaded_mm == &init_mm)) return; + /* Reload the ASID if transitioning into or out of a global ASID */ + if (needs_global_asid_reload(loaded_mm, loaded_mm_asid)) { + switch_mm_irqs_off(NULL, loaded_mm, NULL); + loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); + } + + /* Broadcast ASIDs are always kept up to date with INVLPGB. */ + if (is_global_asid(loaded_mm_asid)) + return; + VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) != loaded_mm->context.ctx_id); @@ -924,6 +987,8 @@ static void flush_tlb_func(void *info) return; } + local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen); + if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID && f->new_tlb_gen <= local_tlb_gen)) { /* @@ -1091,7 +1156,7 @@ STATIC_NOPV void native_flush_tlb_multi(const struct cpumask *cpumask, * up on the new contents of what used to be page tables, while * doing a speculative memory access. */ - if (info->freed_tables) + if (info->freed_tables || in_asid_transition(info->mm)) on_each_cpu_mask(cpumask, flush_tlb_func, (void *)info, true); else on_each_cpu_cond_mask(should_flush_tlb, flush_tlb_func,