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From: Deepak Gupta <debug@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Alexandre Ghiti <alex@ghiti.fr>,
	Masahiro Yamada <masahiroy@kernel.org>,
	 Nathan Chancellor <nathan@kernel.org>,
	 Nicolas Schier <nicolas.schier@linux.dev>,
	 Andrew Morton <akpm@linux-foundation.org>,
	 David Hildenbrand <david@redhat.com>,
	 Lorenzo Stoakes <lorenzo.stoakes@oracle.com>,
	 "Liam R. Howlett" <Liam.Howlett@oracle.com>,
	 Vlastimil Babka <vbabka@suse.cz>,
	Mike Rapoport <rppt@kernel.org>,
	 Suren Baghdasaryan <surenb@google.com>,
	Michal Hocko <mhocko@suse.com>,
	 Nick Desaulniers <nick.desaulniers+lkml@gmail.com>,
	 Bill Wendling <morbo@google.com>,
	Monk Chiang <monk.chiang@sifive.com>,
	 Kito Cheng <kito.cheng@sifive.com>,
	Justin Stitt <justinstitt@google.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	 linux-kbuild@vger.kernel.org, linux-mm@kvack.org,
	llvm@lists.linux.dev,  rick.p.edgecombe@intel.com,
	broonie@kernel.org, cleger@rivosinc.com,
	 samitolvanen@google.com, apatel@ventanamicro.com,
	ajones@ventanamicro.com,  conor.dooley@microchip.com,
	charlie@rivosinc.com, samuel.holland@sifive.com,
	 bjorn@rivosinc.com, fweimer@redhat.com, jeffreyalaw@gmail.com,
	 heinrich.schuchardt@canonical.com, andrew@sifive.com,
	ved@rivosinc.com,  Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH 02/11] riscv: update asm call site in `call_on_irq_stack` to setup correct label
Date: Thu, 24 Jul 2025 16:36:55 -0700	[thread overview]
Message-ID: <20250724-riscv_kcfi-v1-2-04b8fa44c98c@rivosinc.com> (raw)
In-Reply-To: <20250724-riscv_kcfi-v1-0-04b8fa44c98c@rivosinc.com>

Call sites written in asm performing indirect call, they need to setup
label register (t2/x7) with correct label.

Currently first kernel was compiled with `-save-temps` option and
normalized function signature string is captured and then placed at the
asm callsite.

TODO: to write a macro wrapper with toolchain support.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
 arch/riscv/kernel/entry.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 2660faf52232..598e17e800ae 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -389,6 +389,7 @@ SYM_FUNC_START(call_on_irq_stack)
 	load_per_cpu t0, irq_stack_ptr, t1
 	li	t1, IRQ_STACK_SIZE
 	add	sp, t0, t1
+	lui t2, %lpad_hash("FvP7pt_regsE")
 	jalr	a1
 
 	/* Switch back to the thread shadow call stack */

-- 
2.43.0



  parent reply	other threads:[~2025-07-24 23:37 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-24 23:36 [PATCH 00/11] riscv: fine grained hardware assisted kernel control-flow integrity Deepak Gupta
2025-07-24 23:36 ` [PATCH 01/11] riscv: add landing pad for asm routines Deepak Gupta
2025-07-25  6:13   ` Heinrich Schuchardt
2025-07-25 14:10     ` Deepak Gupta
2025-07-25 15:27   ` Sami Tolvanen
2025-07-25 17:01     ` Deepak Gupta
2025-07-24 23:36 ` Deepak Gupta [this message]
2025-07-25  6:23   ` [PATCH 02/11] riscv: update asm call site in `call_on_irq_stack` to setup correct label Heinrich Schuchardt
2025-07-25 14:16     ` Deepak Gupta
2025-07-25 15:33   ` Sami Tolvanen
2025-07-25 16:56     ` Deepak Gupta
2025-07-24 23:36 ` [PATCH 03/11] riscv: indirect jmp in asm that's static in nature to use sw guarded jump Deepak Gupta
2025-07-25  6:26   ` Heinrich Schuchardt
2025-07-24 23:36 ` [PATCH 04/11] riscv: exception handlers can be software guarded transfers Deepak Gupta
2025-07-24 23:36 ` [PATCH 05/11] riscv: enable landing pad enforcement Deepak Gupta
2025-07-25  6:33   ` Heinrich Schuchardt
2025-07-25 14:20     ` Deepak Gupta
2025-07-25 14:43       ` Heinrich Schuchardt
2025-07-24 23:36 ` [PATCH 06/11] mm: Introduce ARCH_HAS_KERNEL_SHADOW_STACK Deepak Gupta
2025-07-26  7:42   ` Mike Rapoport
2025-07-29  0:36     ` Deepak Gupta
2025-07-24 23:37 ` [PATCH 07/11] scs: place init shadow stack in .shadowstack section Deepak Gupta
2025-07-24 23:37 ` [PATCH 08/11] riscv/mm: prepare shadow stack for init task Deepak Gupta
2025-07-24 23:37 ` [PATCH 09/11] riscv: scs: add hardware shadow stack support to scs Deepak Gupta
2025-07-24 23:37 ` [PATCH 10/11] scs: generic scs code updated to leverage hw assisted shadow stack Deepak Gupta
2025-07-25 16:13   ` Sami Tolvanen
2025-07-25 16:42     ` Deepak Gupta
2025-07-25 16:47       ` Deepak Gupta
2025-07-25 16:46     ` Mark Brown
2025-07-28 12:47     ` Will Deacon
2025-07-28 16:37       ` Deepak Gupta
2025-07-25 17:06   ` Edgecombe, Rick P
2025-07-25 17:19     ` Deepak Gupta
2025-07-25 18:05       ` Edgecombe, Rick P
2025-07-28 19:23         ` Deepak Gupta
2025-07-28 21:19           ` Deepak Gupta
2025-07-24 23:37 ` [PATCH 11/11] riscv: Kconfig & Makefile for riscv kernel control flow integrity Deepak Gupta
2025-07-25 11:26   ` Heinrich Schuchardt
2025-07-25 14:23     ` Deepak Gupta
2025-07-25 14:39       ` Heinrich Schuchardt
2025-07-24 23:38 ` [PATCH 00/11] riscv: fine grained hardware assisted kernel control-flow integrity Deepak Gupta

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