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Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Axel Rasmussen , Yuanchu Xie , Chunyan Zhang Subject: Re: [PATCH V12 3/5] riscv: Add RISC-V Svrsw60t59b extension support Message-ID: <20250915-landowner-parsnip-d6778ee7208f@spud> References: <20250915101343.1449546-1-zhangchunyan@iscas.ac.cn> <20250915101343.1449546-4-zhangchunyan@iscas.ac.cn> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="W4tzl3gVaVkMEf2q" Content-Disposition: inline In-Reply-To: <20250915101343.1449546-4-zhangchunyan@iscas.ac.cn> X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: 16DAE120003 X-Stat-Signature: 3fzuueun6hpopj43ion98y6xhkmhs5za X-Rspam-User: X-HE-Tag: 1757955841-57979 X-HE-Meta: U2FsdGVkX19+L0n/YepuhEPGRCwUbHGf7wdAxi+WFGkn6RTWRHt69T3M56UusSmFjB9WbwXrI6+jDMg3pebOoeqnLEmwhQSuSxn1eQM1Ne88Iucnt4dhH9+zldRVQasz9tqmJ7f+cN8KEmLhslY6P2ASr46Z3AHMjyepGtM9TfDH0lzv1NZn1rjNR+9D9ZJ4mWcwI1vDg9ki1aHRP/Wl5jzpdq7W/r8kOPNwXDFAfn6t6usvhLC+rQJad55NUOrQHkXpfBuTxr6Pz3G7H/oA1PdtF3gjxO4a2ZLoL/qvUxgONpL2Y6yZM5Prw80+hg45yYWRpxU4vHBnY0iaVFPzdhN+ocuHmGwD+I+mkQ3J+VbnpG0AJBLgZEpGVbW8DEgu6HalKk2C2fKLBCXGKIJmDGmDZGXk2/ZZYcGYLK24+DzTayWD+uBrk+KyJXNFHsHXUa4xuHJH/7bXxxjXL/TbQxWZunxDQ935M4Bn+57gjaSqXyZv6FJhAxJm8Eb40AL3v84T6pWlIgg5Lxt9qHotW9bGkvLxkI7ma1CcnwZkLVVLjJRto09GU4fPK45o0UaFKTk5GSYCBxtJxLMeBcYOH+e+bNCW7mH0rlXFedU8yUiw8JWIszd2w8I0McrZK4uN4yvQ9a9XSRDFk8xqdSpZuw/KY1IJVK3XssyXPQrx1Ch5mM+qSyiAy2T9OTolCTlUZVq6N7FVsttND7fFRuDQGze4/+UAJLRArcwkeJWyJvhlIavktB7GpkzerRkYhAkNOrIbIvXWlQxDnFwe//+mxrd5qY4hTfnbOJnEqo8Kzcwt2ojj99ugkCKAQy5abdlZZeTTc3CFVcA8FwhuXf8EC9To/cA/VlEAQSuSISda49LveviOvkwyj4SSTye08+Qe+vvEOkcnRr3y30PndlHXhGd3OrrA1/o44yRywGf8bXHGrIS1phGR/WCZjbOvvfSjEXDvKgHgSdg+Kuxfu/j DfXmqWt6 ekjMT0pWXtCjkk3n7vaWyA706zFtHKBGDRP6eWUEdkF6JIBu3CFF5b9AN6ejARSh6q2Rd0adkU6vb/y2ggPrhxn0neTcr/CS67xXRG0JUvDcvBmqr463u39XTUOMH7bWJlAXodUNdWxNZmCp0u15mPeSdU6AwIs5Xs4NyhR0uBgh3a8/YA9yK/k9szjkdNnAzOCHv4hdmKBN1lW+mjNA+JpZ9ZZIoGawgghVnAYUJgXC0xBGZb7kH0cGHJidE+yVu+6L6UhRCFfVX8nD4NqzYXfVKm9SRNmcTSLyVZqqLS7O/ebPdmQHeDKg1IAgWQmoqjxp1T4GfepvVYGv76YnaelMs3zOWU5oWGlDM9HYfm+TdRLewiH+Ue6hQeXNOtXigE7/kuKPXklVAulzF82RQ4aw80ZAo3/ZydxgnMsW6xmnnZh1UHvJjVGaGw/M3SFHJI0um2FMjzNSzuf4TlNBEZnjaMY1y/kYtazmZC+mSRMDz0GO0IWHOR3M1Z3HaYJWCSAq91x2DnGLzBc64CV8qDni5MmHql6rf14ve9QHM3kkdGXGMEUnYkMezxiQMgnxey9fx4bZ2bAjVDDQlPRmYO3nDBpmuvlxZlQ9v X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: --W4tzl3gVaVkMEf2q Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Sep 15, 2025 at 06:13:41PM +0800, Chunyan Zhang wrote: > The Svrsw60t59b extension allows to free the PTE reserved bits 60 > and 59 for software to use. >=20 > Reviewed-by: Alexandre Ghiti > Reviewed-by: Andrew Jones > Signed-off-by: Chunyan Zhang > --- > arch/riscv/Kconfig | 14 ++++++++++++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 3 files changed, 16 insertions(+) >=20 > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 51dcd8eaa243..e1b6a95952c4 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -862,6 +862,20 @@ config RISCV_ISA_ZICBOP > =20 > If you don't know what to do here, say Y. > =20 > +config RISCV_ISA_SVRSW60T59B > + bool "Svrsw60t59b extension support for using PTE bits 60 and 59" > + depends on MMU && 64BIT > + depends on RISCV_ALTERNATIVE > + default y > + help > + Adds support to dynamically detect the presence of the Svrsw60t59b > + extension and enable its usage. > + > + The Svrsw60t59b extension allows to free the PTE reserved bits 60 > + and 59 for software to use. > + > + If you don't know what to do here, say Y. > + > config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI > def_bool y > # https://sourceware.org/git/?p=3Dbinutils-gdb.git;a=3Dcommit;h=3Daed44= 286efa8ae8717a77d94b51ac3614e2ca6dc > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwca= p.h > index affd63e11b0a..f98fcb5c17d5 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -106,6 +106,7 @@ > #define RISCV_ISA_EXT_ZAAMO 97 > #define RISCV_ISA_EXT_ZALRSC 98 > #define RISCV_ISA_EXT_ZICBOP 99 > +#define RISCV_ISA_EXT_SVRSW60T59B 100 > =20 > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > =20 > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeatur= e.c > index 743d53415572..2ba71d2d3fa3 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -539,6 +539,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > + __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B), > __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), If this is not ACPI only, than you need to document this in the extensions dt-binding. --W4tzl3gVaVkMEf2q Content-Type: application/pgp-signature; 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