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Mercier" , =?utf-8?q?Christian_K=C3=B6nig?= , Steven Rostedt , Masami Hiramatsu , Mathieu Desnoyers , Catalin Marinas , Will Deacon Cc: Thierry Reding , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-s390@vger.kernel.org, linux-mm@kvack.org, iommu@lists.linux.dev, linaro-mm-sig@lists.linaro.org, linux-trace-kernel@vger.kernel.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3570; i=treding@nvidia.com; h=from:subject:message-id; bh=GRoiIFMQfM7gzDRzAuvdY2P5ccmj+ETXrFNLv78LxOI=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqRTuFSGQ9dGDN3kzOm9qzarxw9OZw0cL6HePrk 0Jmuoyl0AuJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCakU7hQAKCRDdI6zXfz6z oS/+EAC0wB3gChuITlH2sXNXS95V4q3MybbSfE5oD4mkn+StZvm3vAI3H6Wdr6rx8fe60LuedY1 ghz5YAwiKSOdYiM6OfwagrwPDHgHQVSk3E4CPqiABKXW4cWQrj45IrvuYUv74j4XLe4d86wLPEc XRhz4WxuobfKAmeCp+vP/1AGwYm31jnYqxiEGYGwGax8B/QNjsTHDmN/l8yN0gSCAan2Ebbl6Db B8Y0tocMlvJfkN9Vpy+I8CLl1NVGl8fFDR4rjlxNPMqrXh35zmG9tFZoUZKrXh3gkSueSWXm3Ic dc2rrIVfCdZWUyVVQP3HYvlG3o7ZYoBFQkR9Dgb5utSERxWZywX9+WhXOsfwMTecDydnHHLp9QX 90ACCc5x14rRGWrNQIlX+ybDXW8xM5UH9lHkjZh+d0I2aRyPG+qVnPAuVTSf0X+oVb0gOk853fu g7nObP5ggkU3TL1+l0JvQElWXT27M27tvn33q83T6T1naf8aBXCVi4yvgiz/XxsDYtVZGzCE4c2 8oAnmE+ODLePWMnjAD4liqDajcrofCGaaFuwfGSS30RLIFzaTXxEV5cO2Im7VmVd5cB5Z0riYPB dC4NBuEohrV4cIXBZF9s7vfDIUwZIrcmM41FJPTZ2/Xztxqx9yXCYp3SPR5pN1JqKkpvf+/TC/S 34uWCUo4nfgROIg== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 X-Rspam-User: X-Rspamd-Server: rspam08 X-Rspamd-Queue-Id: B1057140009 X-Stat-Signature: t7wsc7sdwofqdnohxbf8sgrphzeu4frt X-HE-Tag: 1782922127-622983 X-HE-Meta: U2FsdGVkX19iCZJH2ahUDbQOqQX6Mk5pxvlUoX2em2+4E7AooLYDMJgbFmNNnMuQQj2FT4D1lnhHCSlwyrgBIVMp+UQ0ukS2jSMZNIBWasWm1sNfKM3ZV4448BO3Cc6QnSvb22cr4r4PdLoRjyk93S9qIn7Ak2kESXcXv7uae3jtlsO9WCx/YbI5IGbDiVMblFggOYEXPr4T0eKsZiGOyVGOmqyvA812kmH6vGR6zsze/Fz1ksG80HbR9fd2CpVRV56Bm/HIWODLJIViDW+9EHqrOtDVYM7tb767Ek8PaJlZm3tJPLdHxwfpof5SrbfHTmAmnXhR9jFP/NwpoFO08B3X9dssImL5Ub3Z2Rp/ZeBikZqGWZBZ1IovJ77fKuEqhHOYRf/2JaNHhkZuAWuCj/NJVLuC4JZSTlTBbxtyAMFbIM14Cpr2biGjnAq2eiSf3FAHm17CjtcNIbcE0OrC6CPkEjRjiCOHIpi/6IHMV8iu4IqHKj6kGY7O2pjhVfCHpW+nHSEZVuCAK1AUdB6pXsCl1ZGDnYMQAWVj+Pll/Cj/4zWRmw4hJza6KvACSnkil8OCm4DJPkUAsvuVnC8HAx6oHhjih43C2Iv+Vr1peuZUOnykzkWacbbCJXCxUbJ8k8XtRI46DfB3aQ6eXIsy3onJYO6L7343FlG+VxcNZL4obHdUh2TIdhhB836wPG0MOGftu5KsoPZK6RDX+yz4xajhAzyX0yqrvgYEZ4GAKujEOu9/j2QbvAJEMvYX76ijMz35DsExXLkXvZc17u3me5n3b2wroaQtF+OTEs6duEJbT/Z3VcYNbnsY6hHvR2vGFS0pKro5UMVB8SSpROU7/TovNl64L1Ji083kj1pVDbh5iCGO29a6bZIED4z5TKuDXUHCsXd2K9mODnBX1GRFe3yGV58jCRnBBNcB4se5/Nq8QUzwYjiHKTAudbE5URV8IB6Ac8gsHotFzP/8ckN oC/+6gUj BeKmyhbI7Rr1A8WzC2aP6MoCSt8WFCx0emw2O+DQNjlNkl1QzYVn72schoaRJD3WsKgHyYOjgMp7lZkDxBofkJjNvS0VvKUZd2WBQqh75LtB40oGqplUHtDqIxXQLXGX8/ZmoP47ZkBE++5jRu6qoQUl2DGTBFwwzJagsgiVFcre5xP7N4eoTVnTUqKKjP49XdUwf4gamxxuVB1KO4H/AQsb3xxp+hdEwZpW1LwSNYE1t5wrEwgvTWdoz7kpBiO/W/Z6/SLwzsfqGfWZdYQwf8IadDvd/JEVpp9d5KWk85vg8Q+RS9fHoXJCCLw== Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Thierry Reding Add the memory-region and memory-region-names properties to the bindings for the display controllers and the host1x engine found on various Tegra generations. These memory regions are used to access firmware-provided framebuffer memory as well as the video protection region. Signed-off-by: Thierry Reding --- Changes in v3: - document properties for VIC --- .../devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml | 8 ++++++++ .../devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml | 10 ++++++++++ .../devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml | 10 +++++++++- .../bindings/display/tegra/nvidia,tegra20-host1x.yaml | 7 +++++++ 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml index 7200095ef19e..1e27a731ad9a 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml @@ -67,6 +67,14 @@ properties: - const: dma-mem # read - const: write + memory-region: + items: + - description: reference to the video protection memory region + + memory-region-names: + items: + - const: protected + dma-coherent: true additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml index ce4589466a18..881bfbf4764d 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml @@ -57,6 +57,16 @@ properties: - const: dma-mem # read-0 - const: read-1 + memory-region: + minItems: 1 + maxItems: 2 + + memory-region-names: + items: + enum: [ framebuffer, protected ] + minItems: 1 + maxItems: 2 + nvidia,outputs: description: A list of phandles of outputs that this display controller can drive. diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml index 69be95afd562..a012644eeb7d 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml @@ -65,7 +65,15 @@ properties: items: - description: phandle to the core power domain - memory-region: true + memory-region: + minItems: 1 + maxItems: 2 + + memory-region-names: + items: + enum: [ framebuffer, protected ] + minItems: 1 + maxitems: 2 nvidia,head: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml index 3563378a01af..f45be30835a8 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml @@ -96,6 +96,13 @@ properties: items: - description: phandle to the HEG or core power domain + memory-region: + maxItems: 1 + + memory-region-names: + items: + - const: protected + required: - compatible - interrupts -- 2.54.0