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Mercier" , =?utf-8?q?Christian_K=C3=B6nig?= , Steven Rostedt , Masami Hiramatsu , Mathieu Desnoyers , Catalin Marinas , Will Deacon , Chun Ng Cc: Thierry Reding , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-s390@vger.kernel.org, linux-mm@kvack.org, iommu@lists.linux.dev, linaro-mm-sig@lists.linaro.org, linux-trace-kernel@vger.kernel.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3599; i=treding@nvidia.com; h=from:subject:message-id; bh=OEbbK13gPXvWULmBiveQ1tyvB4IMXtbDFRxjKTDEMPs=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqdf/G3HrHADPh/Ggndr9/FKGgb6VqppJr/NF9L +/yWDD6NkuJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCanX/xgAKCRDdI6zXfz6z oYXfD/9Fc1X90Pg5FyqxkYpZ7BOZ2ex2bRQheV4r3UOvlCp0A3WBc5aUjgqIsDyYehKISoSRfSC MDaOdZ8pBxT2BSdBfkArlaMQTMLJ/H567FU74PNLwiarZOfqV901vdBRWFRcONvfoWEPALAHUD7 fpa/p5r1MeLxONleVuq1YFijGYDCC0M3l2WEdAWUsY/9E6PTPaiNwICkoxhY7tKAh9j5mDEgTk3 s4KWx8BNKdWwrqlLuZ4uKQSqp68NysM1LkYSdtPCVVX1lPkqPATpZ1C9X6JmOzu2MiLr+w8CGqM 2O5JxmI51KzP+dmKyHeuIZMkkLaSbOyGa3xqGd7mCO2XvlhoxWewWCe9AI3tFDrjHVe8+t522ig 5h7jCZlBVszKpLcI//08B37OFdg9fe+TqhWuSb0FZ930UUWv3rlpWWCWLnj3R1jMM6lOqKsJeYJ rnP96XEPSLMSJSgWiovbqx8LF1B54UaH1E/K2OSrsJSR/YgLAbeW7w+Wb2ruJHSJvuz6OqGDXBm kTYkvP8vb9494/B3hQRJ1GuYEjAbpGy3YPt/tHDabflvZyUSRws+X/J7b87upvpUMutwwWiPRa5 7qsp2Vdz19nC+0hqoC4HAgHOIS3F3Drl+t1oTGkLadJhjxB8ZboE43Nci/rwf6PQhph/mjvFNYl Tgq5MAtxJ26oLnQ== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 X-Rspamd-Server: rspam07 X-Rspam-User: X-Stat-Signature: jbdtny4ymhhzjzh97pmatacamdrea7q9 X-Rspamd-Queue-Id: 96726140012 X-HE-Tag: 1786118096-919363 X-HE-Meta: U2FsdGVkX1+yQzGBIBmo5HJlfFXISWiOnct50ME0tbFa7sVLLZGi+/KMcEeTFtxOo7aGY7uJ5NwjjF9XPwaeqU5ultreGqss7iaeqIGeaVmD2x4iP5ts1UgxnSZiTGIpjTJh/UzV1IjCafweQnx/yBcxWzccM25f/6l52t5IWVQZrbJve3KqTYuhWq2V5JX7V68HJD/7VICtkIecCb6oLWUyL06n+4DAkRd3Gzrg25mDZ/Nbja09/rnF5fxmGeosT2RcZA5YB3af3fYWuVDp8Am7svKNGRnVR+dF6KAh2aqxbgOBvmD1I/ogc4qHuZXRKfqKDJqT4eGKGxpZ5QO4n9S/oMPaMyWEkKZyJaJIaWpyUO3Q9eyS0aGMXFuIft+wkBRBz5RQmjbjXKKDEoDhjlZX1wBgCjppPhmlzJ+ExxRNEb7RCdMO6Yo/0Wv9HkW/jRDNtuI92RHoaET2kp+hfuT5GoHN0uPFyxIBNdrnvqq0bdYdc4xJPAzS72eAccaF5W1aDkC02uyCZ0Y3Hv/T/eDxgc9c/Lt7wfzKGdaI8YYxh46M/wysobQMPN8mozboTa2XE2mxYD6ZnapBsywMtfXyEdJPRtw756ZvvjCbJ40xsCr4R493dEitfeIwmOnb62jMhG/UWAGsu/IBLPFsqWhS0tQNMiaW5KrlHjk+TnueYQ/ZzrrVklxi+O0gUA0z80pn6fhlBD0ZL5JFlHFVHvxd7/8hqF8vZ0kuxuzd5P5lqRSfDcT6LxUGn18ZsRkwCurbSILbqlLxIAcj3tjNqeaVsZ6AINzKVMP2jBu86oNAHZ97Hk4jRZq9ePwxq78ULR6joVo6ZcjgoTagJ1BIRokWMe8Jx2xUCwvGqehTQ9Bqtb9LlFwG3f3j9Tj6qfy7lQSGXN0U0ts0gVKyAOhavQ76YoRy39LVlZuGGLMSzJ7oKPuf4fxItb3fLKtxNWXb4BMq26kv2cfXEIvnx8E 3lUNTCaP 7rNL0jt+j9eRJAZocCYPLDJuJXPrWBl4w1F2aMHDFp2oHtuxqeBZn1X3ja81ab3oBajcVhftVjQeqs49sUz7t/PGnS1sh8j7PjMDHDfARYlBvJq/NbjTfT+Xlz4gMA0dCIiMNh3QYEvaDDrVcwoXUMGaIlzAjVlqU2HGwlAjDrJe9UPHYt0TZwiErfV72oppm+FqlWidpdD8Ddfqqa0uBE1n7Tfa7MR7q8aoOibqZI48YLZtL+De0OAIrrdy70hMJ2trlIoUwHLjVXcYqXSe7ORMJzb5ZwM94MX/lXpSJ7U7lMuOSCsnN+gr9tw== Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Thierry Reding Add the memory-region and memory-region-names properties to the bindings for the display controllers and the host1x engine found on various Tegra generations. These memory regions are used to access firmware-provided framebuffer memory as well as the video protection region. Signed-off-by: Thierry Reding --- Changes in v4: - typofix Changes in v3: - document properties for VIC --- .../devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml | 8 ++++++++ .../devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml | 10 ++++++++++ .../devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml | 10 +++++++++- .../bindings/display/tegra/nvidia,tegra20-host1x.yaml | 7 +++++++ 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml index bdf981781bd5..fdd3fe9e2547 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml @@ -68,6 +68,14 @@ properties: - const: dma-mem # read - const: write + memory-region: + items: + - description: reference to the video protection memory region + + memory-region-names: + items: + - const: protected + dma-coherent: true additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml index ce4589466a18..881bfbf4764d 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml @@ -57,6 +57,16 @@ properties: - const: dma-mem # read-0 - const: read-1 + memory-region: + minItems: 1 + maxItems: 2 + + memory-region-names: + items: + enum: [ framebuffer, protected ] + minItems: 1 + maxItems: 2 + nvidia,outputs: description: A list of phandles of outputs that this display controller can drive. diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml index 69be95afd562..3bf06dcd6198 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml @@ -65,7 +65,15 @@ properties: items: - description: phandle to the core power domain - memory-region: true + memory-region: + minItems: 1 + maxItems: 2 + + memory-region-names: + items: + enum: [ framebuffer, protected ] + minItems: 1 + maxItems: 2 nvidia,head: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml index 8312b7699cbe..420a1fe5ee80 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml @@ -98,6 +98,13 @@ properties: items: - description: phandle to the HEG or core power domain + memory-region: + maxItems: 1 + + memory-region-names: + items: + - const: protected + required: - compatible - interrupts -- 2.54.0