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bh=/pynzF0A3gZILFAu4wuFpsBCz7QyOd1/gAxCI9UIRGY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gcpjFB6EgLvQQVAFiWJc8GHNZZgIW6kwwYhOxBKre7nN2mtyeWpyRg+BCImi50PGh HfHu0/cnEG81lfmENos4pw2ekoatxNvdJtd035uvXlaYXjm2xhWLAYVijOMiyv38ZT RyFeLq/DuiBES1nv+O5LXQOwfxWnF+hNe4FK8FzU= From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , David Hildenbrand , Mike Rapoport , Andrew Morton , Lorenzo Stoakes , Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, linux-mm@kvack.org Subject: [PATCH V3 1/2] arm64/mm: Move __check_safe_pte_update() Date: Wed, 16 Sep 2026 10:19:32 +0530 Message-ID: <20260916044933.2689426-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260916044933.2689426-1-anshuman.khandual@arm.com> References: <20260916044933.2689426-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: E9694120009 X-Stat-Signature: fh4nj9ttoo6uu7gp4xuscksi53nhwj1p X-Rspam-User: X-HE-Tag: 1789534182-219036 X-HE-Meta: U2FsdGVkX1/dLIUXtQ338uyvVExNVeK7fXFfMGytQOmQRV2gAZrBpGiQ34xhTNKQFRUu2IOZR6hklBtUGofPRdotgEe6JVKenEKBweXkcVy7+Z6pUflp/xyb8I8jlRNTcQAI4dokTD7iGb4YaZgE+Y7knKWD8I0BDDNt6JP48Be9CvqFE9qUjCx5h4cV+/Y2qkMB101a+tmcYgVRrT+1LRl5LI9ENUezJhmISJHV+Ky9f+W/edKHWvciPzsVMmZLtX2zDuCWhQSgx8AREARkCzcyXSX2t8YiP6ePiqxYYRKfxBSP189ABF2AyzvDJyMxmTpgNSF6GxqqNa9uAzOiyldFi1Ll7RRJU6+kpuJ9neIqtFXGyp5KI5ambrYipozzEsyh1a6dDMKed+m45iOPhkzx/X604yhrjq33hE3UVkE2SbXAqDi9QHq+NXG9tC0zble597ERRqTNHWW+oCGitErq6aOZlNbcCGoXbWDvHB4Kh99A73DhuPdCHvksSgFjePGIz/KfuM1JAcfNAqR3rXjXzI3T2X1MJDDFtWytEkUD2xjSm1WLg5T2hK8r/QK3419CBCWwagoWRvQPHFOBHr9eRvlgtvAQ8nKpxz8l1DMbrY4ngemx2FVsdLZclpIuyhHLf+YGmcI4d6w2Wi3CDHjngP+z4vRC/vosstNxotgQ4Lvn0599sspqG5+szeqK9CLPzPGbRb0ltgkDBnRkzU0b05TgDyvvwir7JZuQrEUPpqr5Gvrhz/WZ0myMJ4oyzZQJvDHim77qyPdAS/SuEC3j0Ld3BalhwATx/4Xj9qmj2RU+KT2AZVMKyc4lF+PJCjoEtap0UtdXiAQCJs5N9OILEoVUO1mXuTHEtpL9PbHadJPwfRX+CuU59o2CLtXiiEBrNbsNURIVL+T0/vi8Lj+W+ChrJOcRm1r8s4+mslwX13S605fQUNiQcqKiyV9KMFvfZi5/vZUAY3bP+Fz Cy2mw0po x3zOVCvT3k6bi8uOYxApxSxbiHuuin1nIUelLO1Rvc+UBqSI1b5g7BSpaQxsKg2p2zHmLzX+n1+gFQz0gRAzcfyHwx0sb1Nscq3sbdwbm4kf/3EBAQdNy2N+olY3ZXmWbQCEdLLBltYYhhbbZ+lND4EjmW3M2tWg/cZMT1I2aNVMeGZ4J6crHsoxMb7qRJm98OsIx8n1mBPDYaZNnYauvhpJJTGPwTiitDG9qevaGFh6aampLCA+XsC/2Q1a+zykLbNQhBVAlFTE7CeRLcwXM4l6bdm3kaVtLlxPa0ZXZz7mePS8AHzgQIg+6eQjUebqdOI9dbyi2dptCV7W54HvQ5HWmX4mpoxV3t11WmTWIM60jhw+/R/yT8g2xySr4Muf3g8PQKbqXklqhFFHJJfNknxC/lIUVQkkWKjLU/Jb77Ni3oi4= Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The page table entry print helpers and related macros which are defined in will not be accessible in platform which is basically caused by cycling dependency. Move __check_safe_pte_update() inside arch/arm64/mm/mmu.c as a preparation for subsequent usage of the afore mentioned generic MM helpers. While here drop IS_ENABLED(CONFIG_DEBUG_VM), although wrap __check_safe_pte_update() inside #ifdef CONFIG_DEBUG_VM that preserves the current code optimization which is achieved via the static inline functions. This does not cause any functional change. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: David Hildenbrand (Arm) Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/pgtable.h | 49 ++++---------------------------- arch/arm64/mm/mmu.c | 44 ++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 44 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index e89ec5f4787b..763c5a411d64 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -387,52 +387,13 @@ static inline pte_t __ptep_get(pte_t *ptep) extern void __sync_icache_dcache(pte_t pteval); bool pgattr_change_is_safe(pteval_t old, pteval_t new); -/* - * PTE bits configuration in the presence of hardware Dirty Bit Management - * (PTE_WRITE == PTE_DBM): - * - * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) - * 0 0 | 1 0 0 - * 0 1 | 1 1 0 - * 1 0 | 1 0 1 - * 1 1 | 0 1 x - * - * When hardware DBM is not present, the software PTE_DIRTY bit is updated via - * the page fault mechanism. Checking the dirty status of a pte becomes: - * - * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) - */ - -static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, - pte_t pte) +#ifdef CONFIG_DEBUG_VM +void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, pte_t pte); +#else +static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, pte_t pte) { - pte_t old_pte; - - if (!IS_ENABLED(CONFIG_DEBUG_VM)) - return; - - old_pte = __ptep_get(ptep); - - if (!pte_valid(old_pte) || !pte_valid(pte)) - return; - if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) - return; - - /* - * Check for potential race with hardware updates of the pte - * (__ptep_set_access_flags safely changes valid ptes without going - * through an invalid entry). - */ - VM_WARN_ONCE(!pte_young(pte), - "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", - __func__, pte_val(old_pte), pte_val(pte)); - VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), - "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", - __func__, pte_val(old_pte), pte_val(pte)); - VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), - "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", - __func__, pte_val(old_pte), pte_val(pte)); } +#endif /* CONFIG_DEBUG_VM */ static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) { diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 79d90226fd5d..cb49469707a8 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -2392,4 +2392,48 @@ int arch_set_user_pkey_access(int pkey, unsigned long init_val) return 0; } + +/* + * PTE bits configuration in the presence of hardware Dirty Bit Management + * (PTE_WRITE == PTE_DBM): + * + * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) + * 0 0 | 1 0 0 + * 0 1 | 1 1 0 + * 1 0 | 1 0 1 + * 1 1 | 0 1 x + * + * When hardware DBM is not present, the software PTE_DIRTY bit is updated via + * the page fault mechanism. Checking the dirty status of a pte becomes: + * + * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) + */ +#ifdef CONFIG_DEBUG_VM +void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, pte_t pte) +{ + pte_t old_pte; + + old_pte = __ptep_get(ptep); + + if (!pte_valid(old_pte) || !pte_valid(pte)) + return; + if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) + return; + + /* + * Check for potential race with hardware updates of the pte + * (__ptep_set_access_flags safely changes valid ptes without going + * through an invalid entry). + */ + VM_WARN_ONCE(!pte_young(pte), + "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", + __func__, pte_val(old_pte), pte_val(pte)); + VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), + "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", + __func__, pte_val(old_pte), pte_val(pte)); + VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), + "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", + __func__, pte_val(old_pte), pte_val(pte)); +} +#endif /* CONFIG_DEBUG_VM */ #endif -- 2.43.0