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charset="UTF-8" X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 1A0304000B X-Stat-Signature: gsi9ohbwwyhngtppkotha7f5c4yshd94 X-Rspam-User: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=4.0.1 X-HE-Tag: 1792445486-151460 X-HE-Meta: U2FsdGVkX18YEqlt/HhmWsfYhZxRzhO5hct5w0pUqBUH6HQp9io3kFKyhyoiablpRFayTx4mJncZXbrbsUvGKYRWLackldSJ2qclnjnEbxgJP6e1ODnD1TJ+X46Jgbni7IhQRuBY+FNXjCEx5+05uYZdXDE7bwIYwG1dHbfu2gKSiTBAFhsmgG9ryJ73DsB/jGKDVx21BoPcPf3OdNXAJA3D+DDojpG1lmLevhUZrIgIJe7v2SgGamTqQQw2wSVmyqOBhHN7P8FCyW5abh2cU04TgIdeR/mrD8KjHeAjzg6riqIK+8yj7VjwHqi/aYnh0jJP4pdexpxeCdjUzzm3i3g57xlgIq5wz+6RZ1A2luJdxGBEDRU85sKDrVIa1geBuptSCe8yV2rkcsahnBnBnWr8DeyBz/qXkU99oxcL9Rs2dRxOcvofd3xlj+SWo57vdScLhKr6T7MuXtQ4xVcQz6NPr3loUUZsTQXVkGOpI9PYHxFQUJYNHrQva+jzTZVaz+MDfuQAHHSCJsO10I1YD1gO2kZ1RTET/MOdfREAaT88ax6gyKCqd9iEgyTePp412DPj2ZET4RFOB+djPrht3Mt7t2Z3E2DSDJXrXmGmINkYaB4urHG+Zr0fMLARfOZ5JHxjyHb0dUXR2B/gyW/Z32F7LxSRH2r41mLmmdljHomL4gwpwYttH1LynDKaF8yxYihkWgxzBzcG6OrBzDvBUSRWUmQJuDCEVX+B7gurwYjeIqrwvbYDNFKHPEVCC1VQkO1/OkOGVfwvzaDAfNaeOlrSMqP1pZd3EoKdgND5voiyGwlxToB3SggWZOOkcgJbwf14+5hYgt2jc6YaEYKdrvRARFmd+MAf06C7trbI8vEHd1rRS4BSPCoTM7p0uFGYjbdT75TJ4AZpxjKw/sswIXeeyWbJINlh7KpJtP5W1gz73ndS4oAPm2eW5/GSbs5kMI28rZJhdcDdP+rM/L/ Kyam1vXN 8lpGB6+rxgpRx5KTD8qOFM1CzMVEcLjNPUtaUKgSR4xLSLgtbBawxL72lWSe1gEqje+YSnJpebuRZ8Z7nmH2k83v7MAkk30NgtASg+iGL4WAVnlUe/FnsaxPTWms40wCRofD/APlyP+LNnJH95XnZZfRXPoFKTuqG7XUjFcCoLXbZgXVIWbtZ+C7amlL+Gz6Ir9RCYZhDKeqIfYAGWA2PuuGecZsXg37jb+DUJ0tBf5NEAUl494rwmqa6Soj2sX8opJ4EoUdfOLtANjkBTNoo57yHN9ul6vsiPtiu1bbS9AO+KoVyyWiVdVRirpJu6/wgx9yuAZup4nC+gv5jvVnOnaiQDlh9Bza7BVh7CcMw6lYJ09Cfx56v+SALUftYNQspK4wuGl34UVK8YFd0mDMjZqil8ObjDNrpslnm5uU21GCcNvw/4w4uKHKXF3DaoTcxZSYiYDwcgCFevP3pjdnZ0HDbZYe2mUc0iC17nBfe9dRm0y5F+xTRYYohEY8IRKRlyw7ygg50pINH5w8+mmHz5D30j+0b5WiM+4Pb9sETe0MY+dNg4y3VYAnE3z1wc8/FDwYOnCpLQmDf55xMKwGUG7n8FQ== Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Skip updating the window registers of a bridge in pci_setup_bridge_io(), pci_setup_bridge_mmio(), and pci_setup_bridge_mmio_pref() if they already contain the values being written (ignoring the read-only low bits of the base and limit registers). pci_setup_bridge_io() and pci_setup_bridge_mmio_pref() temporarily disable the I/O and prefetchable memory windows while updating them, since the base and limit of each window are split across multiple registers. This happens even if the window is not changing, e.g. for every bridge whose windows were assigned by firmware and claimed, since __pci_bus_assign_resources_one() calls pci_setup_bridge() on every bridge that is not yet enabled during enumeration. pci_setup_bridge_mmio() updates the memory window with a single write, but skip unchanged writes there too for consistency. This prevents disabling the windows of bridges preserved across Live Update during enumeration, which would disrupt memory transactions targeting preserved devices below them, such as P2PDMA from other preserved devices, or MMIO from VMs whose vCPUs keep running during kexec. Assisted-by: LLM Signed-off-by: David Matlack --- drivers/pci/setup-bus.c | 52 ++++++++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 11 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index e8c94aa1d3c1..4bec76950f46 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -799,8 +799,8 @@ static void pci_setup_bridge_io(struct pci_dev *bridge) struct pci_bus_region region; unsigned long io_mask; u8 io_base_lo, io_limit_lo; - u16 l; - u32 io_upper16; + u16 l, cur_l, l_mask; + u32 io_upper16, cur_io_upper16; io_mask = PCI_IO_RANGE_MASK; if (bridge->io_window_1k) @@ -823,6 +823,18 @@ static void pci_setup_bridge_io(struct pci_dev *bridge) io_upper16 = 0; l = 0x00f0; } + + /* + * Leave the I/O range alone if it is already programmed as needed, + * rather than temporarily disabling it below. The low bits of the I/O + * Base and Limit registers are read-only. + */ + pci_read_config_word(bridge, PCI_IO_BASE, &cur_l); + pci_read_config_dword(bridge, PCI_IO_BASE_UPPER16, &cur_io_upper16); + l_mask = ((u8)io_mask << 8) | (u8)io_mask; + if (!((cur_l ^ l) & l_mask) && cur_io_upper16 == io_upper16) + return; + /* Temporarily disable the I/O range before updating PCI_IO_BASE */ pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); /* Update lower 16 bits of I/O base/limit */ @@ -836,7 +848,7 @@ static void pci_setup_bridge_mmio(struct pci_dev *bridge) struct resource *res; const char *res_name; struct pci_bus_region region; - u32 l; + u32 l, cur_l; /* Set up the top and bottom of the PCI Memory segment for this bus */ res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; @@ -849,6 +861,12 @@ static void pci_setup_bridge_mmio(struct pci_dev *bridge) } else { l = 0x0000fff0; } + + /* The low bits of the Memory Base and Limit registers are read-only */ + pci_read_config_dword(bridge, PCI_MEMORY_BASE, &cur_l); + if (!((cur_l ^ l) & 0xfff0fff0)) + return; + pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); } @@ -857,14 +875,7 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) struct resource *res; const char *res_name; struct pci_bus_region region; - u32 l, bu, lu; - - /* - * Clear out the upper 32 bits of PREF limit. If - * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables - * PREF range, which is ok. - */ - pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); + u32 l, bu, lu, cur_l, cur_bu, cur_lu; /* Set up PREF base/limit */ bu = lu = 0; @@ -882,6 +893,25 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) } else { l = 0x0000fff0; } + + /* + * Leave the PREF range alone if it is already programmed as needed, + * rather than temporarily disabling it below. The low bits of the + * Prefetchable Memory Base and Limit registers are read-only. + */ + pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &cur_l); + pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &cur_bu); + pci_read_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, &cur_lu); + if (!((cur_l ^ l) & 0xfff0fff0) && cur_bu == bu && cur_lu == lu) + return; + + /* + * Clear out the upper 32 bits of PREF limit. If + * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables + * PREF range, which is ok. + */ + pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); + pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); /* Set the upper 32 bits of PREF base & limit */ -- 2.56.0.212.g129ede20d9-goog