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b=iJ+/FIiUC1g6XzTjLwnj6XGPzszrze3zAChLy/4ghxYUT53y7oXHv0nPTPwvAGDd5 Y2ML8NJnlrYt2lZp4bQfZ32ARA3YddcGThJGF730a17Jssq3jO9mf5T3rqeN5ruouD I4htAztWuwFT3frhnZJXAnfuKlg4bXY90JL9XVxaHJj+vct0XNDnPI4zf3YtG1mpGn zhPx7XO/S6IAh7yCPqhX+GbkiHC3HfeGAdTRO/v6xGl6kmktyB+jqDcv64t5YT/PlR g1Ehsq3Zng0Wl69d6k0yGBCU4B2M4HwE6GcK7zfNgw2LbvPJwJf059sp8iyJorxEQA mOubsFL9yiUBA== From: Jisheng Zhang To: Catalin Marinas , Will Deacon , Mark Rutland , Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Dmitry Vyukov , Vincenzo Frascino , Tejun Heo , Dennis Zhou , Christoph Lameter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org Subject: [PATCH v2 1/6] arm64: percpu: Always inline helpers used by noinstr code Date: Mon, 9 Nov 2026 19:44:54 +0800 Message-ID: <20261109114500.20298-2-jszhang@kernel.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261109114500.20298-1-jszhang@kernel.org> References: <20261109114500.20298-1-jszhang@kernel.org> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Stat-Signature: tqffqt57suk6n5dhf4stshcrasm4r13h X-Rspamd-Queue-Id: 2D2A220007 X-Rspam-User: X-Rspamd-Server: rspam08 X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-HE-Tag: 1794225917-630777 X-HE-Meta: U2FsdGVkX1/X/ZD/aBVGNEQx44QUxz4DMaBUWK/7LibrJdMiKs5wbRqzlHvJ4lBlT0FuEQ3IFPsUD3KQjfbkGKHYrlLncnGQ3QdgejZ3+nPSp9nZUg3UvlACP9v488+pdsw42M7kJNsALkSWp5LAVqJOOM4bVeIWx9MEU80N5FYCBB2ZT9ueCzz+h4qkHuZAUzsbxXPSPIVISd7wmR+4lSMlSpVChspTsusMxSBvlMId92Gvm9soEFcRjCgZItls91ItjgPs8yS5khf3qMXGnp5vSXHSmaKMHwJUDbbPCcHTDMCb/wfPPTAluS3J6FCbWwmN57coXZiHdkklIDEhI22BFQMuuJQjnBM9Fyav+OA74FbsJCcxnJ79d3riJI/bcjjB34IPzkt7u6jNptoCxUg6lpfzUs9h689xafdoBuOUgbKJzv0FMp03J6spWAuFsvzMU3Zm/yfP3hVNtxKSIB0kto5zi2lhVYDUj8RhQODdUkjoWBAbCg7wFc/zSyAC/+bJOM5Ma/W3VphR3Tk/pCELIkUqu9LlFKbUy0k0MyOlqBkOilAdTsSjv3J+Y3oodH3Uh9nl58rQ6ZwABrhgo9kbdwS1HVbKm2dRqjov3MpjO7z0Ej9KkttYQ9Zv9BzY9zxo3QYoO8d7hyHXLxLt3NnXI0jFW9lvsevV+l6bONvm/qcJLw9LyZZvBarTyiLwM7jn5Esud6dm8eJrZwJUN5XQ17zKd5ZiHuSHz2cjA3bZsblfLQtAJoKNPjK7zNS6R+agfM/ADSwe5O8195264xF38Sq6t8z7UrU23TAdtQjGLUbvsXAlccJvHFPE1O50nS909DHYz1cvPmomFWxqmT10LbCFoi2hVc90fU/dUHPJbTs/szeWDOAxON6TbnudOja25SZsrmuqbJSCGMdCJB4+MTQt/Pk3H54N6SHXzxMuBVNdZXNEHUJc3brccRZWl0dwWnOcV8j04FIifcN 8Q5VPxZb MCMkW0dDUmHZErSPkXV72nCDmuy7BcQkoZU7jgNt5uIcaLI5qcXi7BaA8wM/ZWf3RUtaQHMj8pU73t0uShTGLUcI0XasNkzUt0iTPicGjTIfM12AIMKq9wSVntS8261uWYWUn7dQ9Au5kAu3cOBy2vXyN4udX0trpvtzsNdHb1sZtzGIquDM0Xovwy1b/udFAEal3lN3TacDxVbsqYrGgmtoATGHEW4Gtpi5B9Rygxy1wZMmsKsnjEmhQXu0kDgXxOxbwr0Yvibd10Ug5np9pbTqzD66+bHHrm7ixldqIhLZGnlyhw0ipGJtw5g== Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The non-instrumentable entry and stack unwinding paths use the per-CPU offset and read helpers. Plain inline does not guarantee inlining, so these helpers can be emitted out of line without inheriting the caller's instrumentation restrictions. In a GCC build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y, __kern_my_cpu_offset() was emitted in .text and called from .noinstr.text. Mark the per-CPU offset and read helpers __always_inline to keep their instructions within their callers. Signed-off-by: Jisheng Zhang Assisted-by: LLM --- arch/arm64/include/asm/percpu.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h index 3cc316091d66..40a327df41cd 100644 --- a/arch/arm64/include/asm/percpu.h +++ b/arch/arm64/include/asm/percpu.h @@ -23,7 +23,7 @@ static inline void set_my_cpu_offset(unsigned long off) :: "r" (off) : "memory"); } -static inline unsigned long __hyp_my_cpu_offset(void) +static __always_inline unsigned long __hyp_my_cpu_offset(void) { /* * Non-VHE hyp code runs with preemption disabled. No need to hazard @@ -37,7 +37,7 @@ static inline unsigned long __hyp_my_cpu_offset(void) "mrs " dst ", tpidr_el2", \ ARM64_HAS_VIRT_HOST_EXTN) -static inline unsigned long __kern_my_cpu_offset(void) +static __always_inline unsigned long __kern_my_cpu_offset(void) { unsigned long off; @@ -129,7 +129,7 @@ static inline unsigned long __kern_my_cpu_offset(void) #endif #define PERCPU_RW_OPS(w, sfx, sz) \ -static inline unsigned long __percpu_read_##sz(void __percpu *pcp) \ +static __always_inline unsigned long __percpu_read_##sz(void __percpu *pcp) \ { \ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \ unsigned long off; \ @@ -149,7 +149,7 @@ static inline unsigned long __percpu_read_##sz(void __percpu *pcp) \ return val; \ } \ \ -static inline void __percpu_write_##sz(void __percpu *pcp, unsigned long val) \ +static __always_inline void __percpu_write_##sz(void __percpu *pcp, unsigned long val) \ { \ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \ unsigned long off; \ @@ -167,7 +167,7 @@ static inline void __percpu_write_##sz(void __percpu *pcp, unsigned long val) \ } #define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ -static inline void \ +static __always_inline void \ __percpu_##name##_case_##sz(void __percpu *pcp, unsigned long val) \ { \ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \ @@ -200,7 +200,7 @@ __percpu_##name##_case_##sz(void __percpu *pcp, unsigned long val) \ } #define __PERCPU_RET_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ -static inline u##sz \ +static __always_inline u##sz \ __percpu_##name##_return_case_##sz(void __percpu *pcp, unsigned long val) \ { \ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \ @@ -270,7 +270,7 @@ PERCPU_RET_OP(add, add, ldadd) #undef PERCPU_RET_OP #define PERCPU_XCHG_OP(w, sfx, sz) \ -static inline unsigned long \ +static __always_inline unsigned long \ __percpu_xchg_case_##sz(void __percpu *pcp, u##sz val) \ { \ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \ @@ -307,7 +307,7 @@ __percpu_xchg_case_##sz(void __percpu *pcp, u##sz val) \ } #define PERCPU_CMPXCHG_OP(w, sfx, sz) \ -static inline unsigned long \ +static __always_inline unsigned long \ __percpu_cmpxchg_case_##sz(void __percpu *pcp, \ u##sz old, \ u##sz new) \ @@ -463,7 +463,7 @@ PERCPU_CMPXCHG_OP(x, , 64) #define this_cpu_cmpxchg64(pcp, o, n) this_cpu_cmpxchg_8(pcp, o, n) -static inline u128 +static __always_inline u128 __percpu_cmpxchg_128(void __percpu *pcp, u128 old, u128 new) { u16 *gprs = ¤t_thread_info()->pcpu_gprs; -- 2.55.0