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[134.134.136.24]) by mx.google.com with ESMTPS id bh2si10791104plb.430.2019.06.10.14.06.10 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Jun 2019 14:06:10 -0700 (PDT) Received-SPF: pass (google.com: domain of yu-cheng.yu@intel.com designates 134.134.136.24 as permitted sender) client-ip=134.134.136.24; Authentication-Results: mx.google.com; spf=pass (google.com: domain of yu-cheng.yu@intel.com designates 134.134.136.24 as permitted sender) smtp.mailfrom=yu-cheng.yu@intel.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jun 2019 14:06:10 -0700 X-ExtLoop1: 1 Received: from yyu32-desk1.sc.intel.com ([143.183.136.147]) by orsmga002.jf.intel.com with ESMTP; 10 Jun 2019 14:06:08 -0700 Message-ID: <328275c9b43c06809c9937c83d25126a6e3efcbd.camel@intel.com> Subject: Re: [PATCH v7 03/14] x86/cet/ibt: Add IBT legacy code bitmap setup function From: Yu-cheng Yu To: Dave Hansen , Andy Lutomirski Cc: Peter Zijlstra , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin Date: Mon, 10 Jun 2019 13:58:01 -0700 In-Reply-To: References: <20190606200926.4029-1-yu-cheng.yu@intel.com> <20190606200926.4029-4-yu-cheng.yu@intel.com> <20190607080832.GT3419@hirez.programming.kicks-ass.net> <20190607174336.GM3436@hirez.programming.kicks-ass.net> <34E0D316-552A-401C-ABAA-5584B5BC98C5@amacapital.net> <7e0b97bf1fbe6ff20653a8e4e147c6285cc5552d.camel@intel.com> <25281DB3-FCE4-40C2-BADB-B3B05C5F8DD3@amacapital.net> <3f19582d-78b1-5849-ffd0-53e8ca747c0d@intel.com> <5aa98999b1343f34828414b74261201886ec4591.camel@intel.com> <0665416d-9999-b394-df17-f2a5e1408130@intel.com> <5c8727dde9653402eea97bfdd030c479d1e8dd99.camel@intel.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.1-2 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Mon, 2019-06-10 at 13:43 -0700, Dave Hansen wrote: > On 6/10/19 1:27 PM, Yu-cheng Yu wrote: > > > > If the loader cannot allocate a big bitmap to cover all 5-level > > > > address space (the bitmap will be large), it can put all legacy lib's > > > > at lower address. We cannot do these easily in the kernel. > > > > > > This is actually an argument to do it in the kernel. The kernel can > > > always allocate the virtual space however it wants, no matter how large. > > > If we hide the bitmap behind a kernel API then we can put it at high > > > 5-level user addresses because we also don't have to worry about the > > > high bits confusing userspace. > > > > We actually tried this. The kernel needs to reserve the bitmap space in the > > beginning for every CET-enabled app, regardless of actual needs. > > I don't think this is a problem. In fact, I think reserving the space > is actually the only sane behavior. If you don't reserve it, you > fundamentally limit where future legacy instructions can go. > > One idea is that we always size the bitmap for the 48-bit addressing > systems. Legacy code probably doesn't _need_ to go in the new address > space, and if we do this we don't have to worry about the gigantic > 57-bit address space bitmap. > > > On each memory request, the kernel then must consider a percentage of > > allocated space in its calculation, and on systems with less memory > > this quickly becomes a problem. > > I'm not sure what you're referring to here? Are you referring to our > overcommit limits? Yes.