From: Rik van Riel <riel@redhat.com>
To: Chris Metcalf <cmetcalf@tilera.com>
Cc: linux-kernel@vger.kernel.org, a.p.zijlstra@chello.nl,
torvalds@linux-foundation.org, aarcange@redhat.com,
tglx@linutronix.de, mingo@elte.hu, akpm@linux-foundation.org,
"David Miller <davem@davemloft.net>" <linux-arch@vger.kernel.org>,
linux-mm@kvack.org, benh@kernel.crashing.org,
hugh.dickins@tiscali.co.uk, mel@csn.ul.ie, npiggin@kernel.dk,
rmk@arm.linux.org.uk, schwidefsky@de.ibm.com
Subject: Re: [PATCH] arch/tile: optimize icache flush
Date: Thu, 10 Mar 2011 18:19:54 -0500 [thread overview]
Message-ID: <4D795C9A.1040509@redhat.com> (raw)
In-Reply-To: <201103102125.p2ALPupL017020@farm-0012.internal.tilera.com>
On 03/10/2011 01:05 PM, Chris Metcalf wrote:
> Tile has incoherent icaches, so they must be explicitly invalidated
> when necessary. Until now we have done so at tlb flush and context
> switch time, which means more invalidation than strictly necessary.
> The new model for icache flush is:
>
> - When we fault in a page as executable, we set an "Exec" bit in the
> "struct page" information; the bit stays set until page free time.
> (We use the arch_1 page bit for our "Exec" bit.)
>
> - At page free time, if the Exec bit is set, we do an icache flush.
> This should happen relatively rarely: e.g., deleting a binary from disk,
> or evicting a binary's pages from the page cache due to memory pressure.
>
> Signed-off-by: Chris Metcalf<cmetcalf@tilera.com>
Nice trick.
Acked-by: Rik van Riel <riel@redhat.com>
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next prev parent reply other threads:[~2011-03-10 23:20 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-02 17:59 [RFC][PATCH 0/6] mm: Unify TLB gather implementations Peter Zijlstra
2011-03-02 17:59 ` [RFC][PATCH 1/6] mm: Optimize fullmm TLB flushing Peter Zijlstra
2011-03-02 17:59 ` [RFC][PATCH 2/6] mm: Change flush_tlb_range() to take an mm_struct Peter Zijlstra
2011-03-02 19:19 ` Linus Torvalds
2011-03-02 20:58 ` Rik van Riel
2011-03-02 21:40 ` Peter Zijlstra
2011-03-02 21:47 ` David Miller
2011-03-03 17:22 ` Chris Metcalf
2011-03-03 18:45 ` David Miller
2011-03-03 18:56 ` Chris Metcalf
2011-03-10 18:05 ` [PATCH] arch/tile: optimize icache flush Chris Metcalf
2011-03-10 23:19 ` Rik van Riel [this message]
2011-03-02 17:59 ` [RFC][PATCH 3/6] mm: Provide generic range tracking and flushing Peter Zijlstra
2011-03-02 17:59 ` [RFC][PATCH 4/6] arm, mm: Convert arm to generic tlb Peter Zijlstra
2011-03-09 15:16 ` Catalin Marinas
2011-03-09 15:19 ` Peter Zijlstra
2011-03-09 15:36 ` Catalin Marinas
2011-03-09 15:39 ` Peter Zijlstra
2011-03-09 15:48 ` Peter Zijlstra
2011-03-09 16:34 ` Catalin Marinas
2012-05-17 3:05 ` Paul Mundt
2012-05-17 9:30 ` Catalin Marinas
2012-05-17 9:39 ` Catalin Marinas
2012-05-17 9:51 ` Russell King
2012-05-17 11:28 ` Peter Zijlstra
2012-05-17 12:14 ` Catalin Marinas
2012-05-17 16:00 ` Catalin Marinas
2012-05-17 16:24 ` Peter Zijlstra
2012-05-17 16:33 ` Peter Zijlstra
2012-05-17 16:44 ` Peter Zijlstra
2012-05-17 16:59 ` Peter Zijlstra
2012-05-17 17:01 ` Catalin Marinas
2012-05-17 17:11 ` Peter Zijlstra
2012-05-21 7:47 ` Martin Schwidefsky
2012-05-17 17:22 ` Russell King
2012-05-17 18:31 ` Catalin Marinas
2011-03-02 17:59 ` [RFC][PATCH 5/6] ia64, mm: Convert ia64 " Peter Zijlstra
2011-03-02 17:59 ` [RFC][PATCH 6/6] sh, mm: Convert sh " Peter Zijlstra
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