From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from psmtp.com (na3sys010amx202.postini.com [74.125.245.202]) by kanga.kvack.org (Postfix) with SMTP id 733666B0068 for ; Fri, 15 Jun 2012 11:14:19 -0400 (EDT) Received: from /spool/local by e9.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 15 Jun 2012 11:14:17 -0400 Received: from d01relay04.pok.ibm.com (d01relay04.pok.ibm.com [9.56.227.236]) by d01dlp01.pok.ibm.com (Postfix) with ESMTP id 2B69538C806E for ; Fri, 15 Jun 2012 11:13:21 -0400 (EDT) Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by d01relay04.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q5FFDJ8o188308 for ; Fri, 15 Jun 2012 11:13:20 -0400 Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q5FFDIHo018787 for ; Fri, 15 Jun 2012 09:13:19 -0600 Message-ID: <4FDB5107.3000308@linux.vnet.ibm.com> Date: Fri, 15 Jun 2012 10:13:11 -0500 From: Seth Jennings MIME-Version: 1.0 Subject: Re: [PATCH v2 3/3] x86: Support local_flush_tlb_kernel_range References: <1337133919-4182-1-git-send-email-minchan@kernel.org> <1337133919-4182-3-git-send-email-minchan@kernel.org> <4FB4B29C.4010908@kernel.org> <1337266310.4281.30.camel@twins> In-Reply-To: <1337266310.4281.30.camel@twins> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: Peter Zijlstra Cc: Minchan Kim , Greg Kroah-Hartman , Nitin Gupta , Dan Magenheimer , linux-kernel@vger.kernel.org, linux-mm@kvack.org, Thomas Gleixner , Ingo Molnar , Tejun Heo , David Howells , x86@kernel.org, Nick Piggin On 05/17/2012 09:51 AM, Peter Zijlstra wrote: > On Thu, 2012-05-17 at 17:11 +0900, Minchan Kim wrote: >>> +++ b/arch/x86/include/asm/tlbflush.h >>> @@ -172,4 +172,16 @@ static inline void flush_tlb_kernel_range(unsigned long start, >>> flush_tlb_all(); >>> } >>> >>> +static inline void local_flush_tlb_kernel_range(unsigned long start, >>> + unsigned long end) >>> +{ >>> + if (cpu_has_invlpg) { >>> + while (start < end) { >>> + __flush_tlb_single(start); >>> + start += PAGE_SIZE; >>> + } >>> + } else >>> + local_flush_tlb(); >>> +} > > > It would be much better if you wait for Alex Shi's patch to mature. > doing the invlpg thing for ranges is not an unconditional win. >>From what I can tell Alex's patches have stalled. The last post was v6 on 5/17 and there wasn't a single reply to them afaict. According to Alex's investigation of this "tipping point", it seems that a good generic value is 8. In other words, on most x86 hardware, it is cheaper to flush up to 8 tlb entries one by one rather than doing a complete flush. So we can do something like: if (cpu_has_invlpg && (end - start)/PAGE_SIZE <= 8) { while (start < end) { Would this be acceptable? Thanks, Seth -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org