From: Dave Hansen <dave.hansen@intel.com>
To: Rik van Riel <riel@surriel.com>, x86@kernel.org
Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org,
dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com,
nadav.amit@gmail.com, thomas.lendacky@amd.com,
kernel-team@meta.com, linux-mm@kvack.org,
akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com,
mhklinux@outlook.com, andrew.cooper3@citrix.com,
Manali.Shukla@amd.com, mingo@kernel.org
Subject: Re: [PATCH v14 04/13] x86/mm: use INVLPGB for kernel TLB flushes
Date: Fri, 28 Feb 2025 11:00:52 -0800 [thread overview]
Message-ID: <4c2144a4-8889-483b-bb16-4d361d1d3d90@intel.com> (raw)
In-Reply-To: <20250226030129.530345-5-riel@surriel.com>
On 2/25/25 19:00, Rik van Riel wrote:
> Use broadcast TLB invalidation for kernel addresses when available.
>
> Remove the need to send IPIs for kernel TLB flushes.
Nit: the changelog doesn't address the refactoring.
*Ideally*, you'd create the helpers and move the code there in one patch
and then actually "use INVLPGB for kernel TLB flushes" in the next. It's
compact enough here that it's not a deal breaker.
> +static void invlpgb_kernel_range_flush(struct flush_tlb_info *info)
> +{
> + unsigned long addr, nr;
> +
> + for (addr = info->start; addr < info->end; addr += nr << PAGE_SHIFT) {
> + nr = (info->end - addr) >> PAGE_SHIFT;
> + nr = clamp_val(nr, 1, invlpgb_count_max);
> + invlpgb_flush_addr_nosync(addr, nr);
> + }
> + __tlbsync();
> +}
This needs a comment or two. Explaining that the function can take large
sizes:
/*
* Flush an arbitrarily large range of memory with INVLPGB
*/
But that the _instruction_ can not is important. This would be great in
the loop just above the clamp:
/*
* INVLPGB has a limit on the size of ranges
* it can flush. Break large flushes up.
*/
> static void do_kernel_range_flush(void *info)
> {
> struct flush_tlb_info *f = info;
> @@ -1087,6 +1099,22 @@ static void do_kernel_range_flush(void *info)
> flush_tlb_one_kernel(addr);
> }
>
> +static void kernel_tlb_flush_all(struct flush_tlb_info *info)
> +{
> + if (cpu_feature_enabled(X86_FEATURE_INVLPGB))
> + invlpgb_flush_all();
> + else
> + on_each_cpu(do_flush_tlb_all, NULL, 1);
> +}
> +
> +static void kernel_tlb_flush_range(struct flush_tlb_info *info)
> +{
> + if (cpu_feature_enabled(X86_FEATURE_INVLPGB))
> + invlpgb_kernel_range_flush(info);
> + else
> + on_each_cpu(do_kernel_range_flush, info, 1);
> +}
> +
> void flush_tlb_kernel_range(unsigned long start, unsigned long end)
> {
> struct flush_tlb_info *info;
> @@ -1097,9 +1125,9 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
> TLB_GENERATION_INVALID);
>
> if (info->end == TLB_FLUSH_ALL)
> - on_each_cpu(do_flush_tlb_all, NULL, 1);
> + kernel_tlb_flush_all(info);
> else
> - on_each_cpu(do_kernel_range_flush, info, 1);
> + kernel_tlb_flush_range(info);
>
> put_flush_tlb_info();
> }
But the structure of this code is much better than previous versions.
With the comments fixed:
Acked-by: Dave Hansen <dave.hansen@intel.com>
next prev parent reply other threads:[~2025-02-28 19:00 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-26 3:00 [PATCH v14 00/13] AMD broadcast TLB invalidation Rik van Riel
2025-02-26 3:00 ` [PATCH v14 01/13] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-09-02 15:44 ` [BUG] x86/mm: regression after 4a02ed8e1cc3 Giovanni Cabiddu
2025-09-02 15:50 ` Dave Hansen
2025-09-02 16:08 ` Nadav Amit
2025-09-02 16:11 ` Dave Hansen
2025-09-03 14:00 ` Rik van Riel
2025-09-02 16:05 ` Jann Horn
2025-09-02 16:13 ` Jann Horn
2025-09-03 14:18 ` Nadav Amit
2025-09-03 14:42 ` Jann Horn
2025-09-02 16:31 ` Jann Horn
2025-09-02 16:57 ` Giovanni Cabiddu
2025-02-26 3:00 ` [PATCH v14 02/13] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-02-28 16:21 ` Borislav Petkov
2025-02-28 19:27 ` Borislav Petkov
2025-02-26 3:00 ` [PATCH v14 03/13] x86/mm: add INVLPGB support code Rik van Riel
2025-02-28 18:46 ` Borislav Petkov
2025-02-28 18:51 ` Dave Hansen
2025-02-28 19:47 ` Borislav Petkov
2025-03-03 18:41 ` Dave Hansen
2025-03-03 19:23 ` Dave Hansen
2025-03-04 11:00 ` Borislav Petkov
2025-03-04 15:10 ` Dave Hansen
2025-03-04 16:19 ` Borislav Petkov
2025-03-04 16:57 ` Dave Hansen
2025-03-04 21:12 ` Borislav Petkov
2025-02-26 3:00 ` [PATCH v14 04/13] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-02-28 19:00 ` Dave Hansen [this message]
2025-02-28 21:43 ` Borislav Petkov
2025-02-26 3:00 ` [PATCH v14 05/13] x86/mm: use INVLPGB in flush_tlb_all Rik van Riel
2025-02-28 19:18 ` Dave Hansen
2025-03-01 12:20 ` Borislav Petkov
2025-03-01 15:54 ` Rik van Riel
2025-02-28 22:20 ` Borislav Petkov
2025-02-26 3:00 ` [PATCH v14 06/13] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-02-28 18:57 ` Borislav Petkov
2025-02-26 3:00 ` [PATCH v14 07/13] x86/mm: add global ASID allocation helper functions Rik van Riel
2025-03-02 7:06 ` Borislav Petkov
2025-02-26 3:00 ` [PATCH v14 08/13] x86/mm: global ASID context switch & TLB flush handling Rik van Riel
2025-03-02 7:58 ` Borislav Petkov
2025-02-26 3:00 ` [PATCH v14 09/13] x86/mm: global ASID process exit helpers Rik van Riel
2025-03-02 12:38 ` Borislav Petkov
2025-03-02 13:53 ` Rik van Riel
2025-03-03 10:16 ` Borislav Petkov
2025-02-26 3:00 ` [PATCH v14 10/13] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-03-03 10:57 ` Borislav Petkov
2025-02-26 3:00 ` [PATCH v14 11/13] x86/mm: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-03-03 11:46 ` Borislav Petkov
2025-03-03 21:47 ` Dave Hansen
2025-03-04 11:52 ` Borislav Petkov
2025-03-04 15:24 ` Dave Hansen
2025-03-04 12:52 ` Brendan Jackman
2025-03-04 14:11 ` Borislav Petkov
2025-03-04 15:33 ` Brendan Jackman
2025-03-04 17:51 ` Dave Hansen
2025-02-26 3:00 ` [PATCH v14 12/13] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-02-26 3:00 ` [PATCH v14 13/13] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-03-03 22:40 ` Dave Hansen
2025-03-04 11:53 ` Borislav Petkov
2025-03-03 12:42 ` [PATCH v14 00/13] AMD broadcast TLB invalidation Borislav Petkov
2025-03-03 13:29 ` Borislav Petkov
2025-03-04 12:04 ` [PATCH] x86/mm: Always set the ASID valid bit for the INVLPGB instruction Borislav Petkov
2025-03-04 12:43 ` Borislav Petkov
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