From: Ira Weiny <ira.weiny@intel.com>
To: Dan Williams <dan.j.williams@intel.com>, <linux-cxl@vger.kernel.org>
Cc: <dave.hansen@linux.intel.com>, <linux-mm@kvack.org>,
<linux-acpi@vger.kernel.org>
Subject: Re: [PATCH 11/18] cxl/region: Add region autodiscovery
Date: Mon, 6 Feb 2023 11:02:14 -0800 [thread overview]
Message-ID: <63e14eb6b350b_fa32929429@iweiny-mobl.notmuch> (raw)
In-Reply-To: <167564540972.847146.17096178433176097831.stgit@dwillia2-xfh.jf.intel.com>
Dan Williams wrote:
[snip]
> +
> +static int cmp_decode_pos(const void *a, const void *b)
> +{
> + struct cxl_endpoint_decoder *cxled_a = *(typeof(cxled_a) *)a;
> + struct cxl_endpoint_decoder *cxled_b = *(typeof(cxled_b) *)b;
> + struct cxl_memdev *cxlmd_a = cxled_to_memdev(cxled_a);
> + struct cxl_memdev *cxlmd_b = cxled_to_memdev(cxled_b);
> + struct cxl_port *port_a = cxled_to_port(cxled_a);
> + struct cxl_port *port_b = cxled_to_port(cxled_b);
> + struct cxl_port *iter_a, *iter_b;
> +
> + /* Exit early if any prior sorting failed */
> + if (cxled_a->pos < 0 || cxled_b->pos < 0)
> + return 0;
> +
> + /*
> + * Walk up the hierarchy to find a shared port, find the decoder
> + * that maps the range, compare the relative position of those
> + * dport mappings.
> + */
> + for (iter_a = port_a; iter_a; iter_a = next_port(iter_a)) {
> + struct cxl_port *next_a, *next_b, *port;
> + struct cxl_switch_decoder *cxlsd;
> +
> + next_a = next_port(iter_a);
> + for (iter_b = port_b; iter_b; iter_b = next_port(iter_b)) {
> + int a_pos, b_pos, result;
> + struct device *dev;
> + unsigned int seq;
> +
> + next_b = next_port(iter_b);
> + if (next_a != next_b)
> + continue;
> + if (!next_a)
> + goto out;
To me this check makes more sense before the inner loop.
> + port = next_a;
> + dev = device_find_child(&port->dev, cxled_a,
> + decoder_match_range);
> + if (!dev) {
> + struct range *range = &cxled_a->cxld.hpa_range;
> +
> + dev_err(port->uport,
> + "failed to find decoder that maps %#llx-:%#llx\n",
> + range->start, range->end);
> + cxled_a->pos = -1;
> + return 0;
> + }
> +
> + cxlsd = to_cxl_switch_decoder(dev);
> + do {
> + seq = read_seqbegin(&cxlsd->target_lock);
> + find_positions(cxlsd, iter_a, iter_b, &a_pos,
> + &b_pos);
> + } while (read_seqretry(&cxlsd->target_lock, seq));
> +
> + if (a_pos < 0 || b_pos < 0) {
> + dev_err(port->uport,
> + "failed to find shared decoder for %s and %s\n",
> + dev_name(cxlmd_a->dev.parent),
> + dev_name(cxlmd_b->dev.parent));
> + cxled_a->pos = -1;
> + result = 0;
> + } else {
> + result = a_pos - b_pos;
> + dev_dbg(port->uport, "%s: %s comes %s %s\n",
> + dev_name(&cxlsd->cxld.dev),
> + dev_name(cxlmd_a->dev.parent),
> + result < 0 ? "before" : "after",
> + dev_name(cxlmd_b->dev.parent));
> + }
> +
> + put_device(dev);
> +
> + return result;
> + }
> + }
> +out:
> + dev_err(cxlmd_a->dev.parent, "failed to find shared port with %s\n",
> + dev_name(cxlmd_b->dev.parent));
> + cxled_a->pos = -1;
> + return 0;
> +}
> +
[snip]
> @@ -1500,8 +1766,8 @@ static int detach_target(struct cxl_region *cxlr, int pos)
> return rc;
> }
>
> -static size_t store_targetN(struct cxl_region *cxlr, const char *buf, int pos,
> - size_t len)
> +static ssize_t store_targetN(struct cxl_region *cxlr, const char *buf, int pos,
> + size_t len)
Is this a separate fix?
> {
> int rc;
>
[snip]
> +
> +/* Establish an empty region covering the given HPA range */
> +static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
> + struct cxl_endpoint_decoder *cxled)
Rather than a comment would this be better named construct_empty_region()?
Ira
next prev parent reply other threads:[~2023-02-06 19:02 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 1:02 [PATCH 00/18] CXL RAM and the 'Soft Reserved' => 'System RAM' default Dan Williams
2023-02-06 1:02 ` [PATCH 01/18] cxl/Documentation: Update references to attributes added in v6.0 Dan Williams
2023-02-06 15:17 ` Jonathan Cameron
2023-02-06 16:37 ` Gregory Price
2023-02-06 17:27 ` [PATCH 1/18] " Davidlohr Bueso
2023-02-06 19:15 ` [PATCH 01/18] " Ira Weiny
2023-02-06 21:04 ` Dave Jiang
2023-02-09 0:20 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 02/18] cxl/region: Add a mode attribute for regions Dan Williams
2023-02-06 15:46 ` Jonathan Cameron
2023-02-06 17:47 ` Dan Williams
2023-02-06 16:39 ` Gregory Price
2023-02-06 19:16 ` Ira Weiny
2023-02-06 21:05 ` Dave Jiang
2023-02-09 0:22 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 03/18] cxl/region: Support empty uuids for non-pmem regions Dan Williams
2023-02-06 15:54 ` Jonathan Cameron
2023-02-06 18:07 ` Dan Williams
2023-02-06 19:22 ` Ira Weiny
2023-02-06 19:35 ` Dan Williams
2023-02-09 0:24 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 04/18] cxl/region: Validate region mode vs decoder mode Dan Williams
2023-02-06 16:02 ` Jonathan Cameron
2023-02-06 18:14 ` Dan Williams
2023-02-06 16:44 ` Gregory Price
2023-02-06 21:51 ` Dan Williams
2023-02-06 19:55 ` Gregory Price
2023-02-06 19:23 ` Ira Weiny
2023-02-06 22:16 ` Dave Jiang
2023-02-09 0:25 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 05/18] cxl/region: Add volatile region creation support Dan Williams
2023-02-06 16:18 ` Jonathan Cameron
2023-02-06 18:19 ` Dan Williams
2023-02-06 16:55 ` Gregory Price
2023-02-06 21:57 ` Dan Williams
2023-02-06 19:56 ` Gregory Price
2023-02-06 19:25 ` Ira Weiny
2023-02-06 22:31 ` Dave Jiang
2023-02-06 22:37 ` Dan Williams
2023-02-09 1:02 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 06/18] cxl/region: Refactor attach_target() for autodiscovery Dan Williams
2023-02-06 17:06 ` Jonathan Cameron
2023-02-06 18:48 ` Dan Williams
2023-02-06 19:26 ` Ira Weiny
2023-02-06 22:41 ` Dave Jiang
2023-02-09 1:09 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 07/18] cxl/region: Move region-position validation to a helper Dan Williams
2023-02-06 17:44 ` Ira Weiny
2023-02-06 19:15 ` Dan Williams
2023-02-08 12:30 ` Jonathan Cameron
2023-02-09 4:09 ` Dan Williams
2023-02-09 4:26 ` Dan Williams
2023-02-09 11:07 ` Jonathan Cameron
2023-02-09 20:52 ` Dan Williams
2023-02-09 19:45 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 08/18] kernel/range: Uplevel the cxl subsystem's range_contains() helper Dan Williams
2023-02-06 17:02 ` Gregory Price
2023-02-06 22:01 ` Dan Williams
2023-02-06 19:28 ` Ira Weiny
2023-02-06 23:41 ` Dave Jiang
2023-02-08 12:32 ` Jonathan Cameron
2023-02-09 19:47 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 09/18] cxl/region: Enable CONFIG_CXL_REGION to be toggled Dan Williams
2023-02-06 17:03 ` Gregory Price
2023-02-06 23:57 ` Dave Jiang
2023-02-08 12:36 ` Jonathan Cameron
2023-02-09 20:17 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 10/18] cxl/region: Fix passthrough-decoder detection Dan Williams
2023-02-06 5:38 ` Greg KH
2023-02-06 17:22 ` Dan Williams
2023-02-07 0:00 ` Dave Jiang
2023-02-08 12:44 ` Jonathan Cameron
2023-02-09 20:28 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 11/18] cxl/region: Add region autodiscovery Dan Williams
2023-02-06 19:02 ` Ira Weiny [this message]
2023-02-07 23:54 ` Dave Jiang
2023-02-08 17:07 ` Jonathan Cameron
2023-02-09 4:07 ` Dan Williams
2023-02-06 1:03 ` [PATCH 12/18] tools/testing/cxl: Define a fixed volatile configuration to parse Dan Williams
2023-02-08 17:31 ` Jonathan Cameron
2023-02-09 20:50 ` Dan Williams
2023-02-06 1:03 ` [PATCH 13/18] dax/hmem: Move HMAT and Soft reservation probe initcall level Dan Williams
2023-02-06 1:03 ` [PATCH 14/18] dax/hmem: Drop unnecessary dax_hmem_remove() Dan Williams
2023-02-06 17:15 ` Gregory Price
2023-02-08 17:33 ` Jonathan Cameron
2023-02-06 1:03 ` [PATCH 15/18] dax/hmem: Convey the dax range via memregion_info() Dan Williams
2023-02-08 17:35 ` Jonathan Cameron
2023-02-06 1:03 ` [PATCH 16/18] dax/hmem: Move hmem device registration to dax_hmem.ko Dan Williams
2023-02-06 1:04 ` [PATCH 17/18] dax: Assign RAM regions to memory-hotplug by default Dan Williams
2023-02-06 17:26 ` Gregory Price
2023-02-06 22:15 ` Dan Williams
2023-02-06 19:05 ` Gregory Price
2023-02-06 23:20 ` Dan Williams
2023-02-06 1:04 ` [PATCH 18/18] cxl/dax: Create dax devices for CXL RAM regions Dan Williams
2023-02-06 5:36 ` [PATCH 00/18] CXL RAM and the 'Soft Reserved' => 'System RAM' default Gregory Price
2023-02-06 16:40 ` Davidlohr Bueso
2023-02-06 18:23 ` Dan Williams
2023-02-06 17:29 ` Dan Williams
2023-02-06 17:18 ` Davidlohr Bueso
[not found] ` <CGME20230208173730uscas1p2af3a9eeb8946dfa607b190c079a49653@uscas1p2.samsung.com>
2023-02-08 17:37 ` Fan Ni
2023-02-09 4:56 ` Dan Williams
2023-02-13 12:13 ` David Hildenbrand
2023-02-14 18:45 ` Dan Williams
2023-02-14 18:27 ` Gregory Price
2023-02-14 18:39 ` Dan Williams
2023-02-14 19:01 ` Gregory Price
2023-02-14 21:18 ` Jonathan Cameron
2023-02-14 21:51 ` Gregory Price
2023-02-14 21:54 ` Gregory Price
2023-02-15 10:03 ` Jonathan Cameron
2023-02-18 9:47 ` Gregory Price
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