From: Dan Williams <dan.j.williams@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dave.hansen@linux.intel.com>,
<linux-mm@kvack.org>, <linux-acpi@vger.kernel.org>
Subject: Re: [PATCH 12/18] tools/testing/cxl: Define a fixed volatile configuration to parse
Date: Thu, 9 Feb 2023 12:50:50 -0800 [thread overview]
Message-ID: <63e55caaced8b_36c7294e2@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20230208173149.000043a2@Huawei.com>
Jonathan Cameron wrote:
> On Sun, 05 Feb 2023 17:03:35 -0800
> Dan Williams <dan.j.williams@intel.com> wrote:
>
> > Take two endpoints attached to the first switch on the first host-bridge
> > in the cxl_test topology and define a pre-initialized region. This is a
> > x2 interleave underneath a x1 CXL Window.
> >
> > $ modprobe cxl_test
> > $ # cxl list -Ru
> > {
> > "region":"region3",
> > "resource":"0xf010000000",
> > "size":"512.00 MiB (536.87 MB)",
> > "interleave_ways":2,
> > "interleave_granularity":4096,
> > "decode_state":"commit"
> > }
> >
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> > ---
> > drivers/cxl/core/core.h | 3 -
> > drivers/cxl/core/hdm.c | 3 +
> > drivers/cxl/core/port.c | 4 +
> > drivers/cxl/cxl.h | 4 +
> > drivers/cxl/cxlmem.h | 3 +
> > tools/testing/cxl/test/cxl.c | 146 +++++++++++++++++++++++++++++++++++++++---
> > 6 files changed, 148 insertions(+), 15 deletions(-)
> >
>
> > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> > index 8130430ffbcf..8d0895cbae93 100644
> > --- a/drivers/cxl/core/port.c
> > +++ b/drivers/cxl/core/port.c
> > @@ -458,6 +458,7 @@ bool is_switch_decoder(struct device *dev)
> > {
> > return is_root_decoder(dev) || dev->type == &cxl_decoder_switch_type;
> > }
> > +EXPORT_SYMBOL_NS_GPL(is_switch_decoder, CXL);
> >
> > struct cxl_decoder *to_cxl_decoder(struct device *dev)
> > {
> > @@ -485,6 +486,7 @@ struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev)
> > return NULL;
> > return container_of(dev, struct cxl_switch_decoder, cxld.dev);
> > }
> > +EXPORT_SYMBOL_NS_GPL(to_cxl_switch_decoder, CXL);
> >
> > static void cxl_ep_release(struct cxl_ep *ep)
> > {
> > @@ -528,7 +530,7 @@ static const struct device_type cxl_port_type = {
> >
> > bool is_cxl_port(struct device *dev)
> > {
> > - return dev->type == &cxl_port_type;
> > + return dev && dev->type == &cxl_port_type;
>
> Adding that protection just for mocking seems a bit nasty.
> Could you push the sanity check out to the caller or am I missing something?
> Perhaps worth calling out the reason we'd call this on a NULL dev with a comment
> or similar.
Oh, that was probably a bug fix for an interim version of cxl_test that
I neglected to come back and clean up. A "while (port)" loop should not
walk off the top of a port->dev.parent chain.
Confirmed that the self-test still passes with this extra check gone.
> > }
> > EXPORT_SYMBOL_NS_GPL(is_cxl_port, CXL);
> >
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index 9b3765c5c81a..4c6ee6c96f23 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -452,6 +452,7 @@ struct cxl_region_params {
> > * struct cxl_region - CXL region
> > * @dev: This region's device
> > * @id: This region's id. Id is globally unique across all regions
> > + * @fixed: At least one decoder in this region was locked down at init
> > * @mode: Endpoint decoder allocation / access mode
> > * @type: Endpoint decoder target type
> > * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown
> > @@ -462,6 +463,7 @@ struct cxl_region_params {
> > struct cxl_region {
> > struct device dev;
> > int id;
> > + bool fixed;
>
> I was wondering why a mocking patch was changing the region state structure...
> It isn't - this isn't used that I can find.
Another interim hack that I failed to cleanup before posting.
next prev parent reply other threads:[~2023-02-09 20:51 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 1:02 [PATCH 00/18] CXL RAM and the 'Soft Reserved' => 'System RAM' default Dan Williams
2023-02-06 1:02 ` [PATCH 01/18] cxl/Documentation: Update references to attributes added in v6.0 Dan Williams
2023-02-06 15:17 ` Jonathan Cameron
2023-02-06 16:37 ` Gregory Price
2023-02-06 17:27 ` [PATCH 1/18] " Davidlohr Bueso
2023-02-06 19:15 ` [PATCH 01/18] " Ira Weiny
2023-02-06 21:04 ` Dave Jiang
2023-02-09 0:20 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 02/18] cxl/region: Add a mode attribute for regions Dan Williams
2023-02-06 15:46 ` Jonathan Cameron
2023-02-06 17:47 ` Dan Williams
2023-02-06 16:39 ` Gregory Price
2023-02-06 19:16 ` Ira Weiny
2023-02-06 21:05 ` Dave Jiang
2023-02-09 0:22 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 03/18] cxl/region: Support empty uuids for non-pmem regions Dan Williams
2023-02-06 15:54 ` Jonathan Cameron
2023-02-06 18:07 ` Dan Williams
2023-02-06 19:22 ` Ira Weiny
2023-02-06 19:35 ` Dan Williams
2023-02-09 0:24 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 04/18] cxl/region: Validate region mode vs decoder mode Dan Williams
2023-02-06 16:02 ` Jonathan Cameron
2023-02-06 18:14 ` Dan Williams
2023-02-06 16:44 ` Gregory Price
2023-02-06 21:51 ` Dan Williams
2023-02-06 19:55 ` Gregory Price
2023-02-06 19:23 ` Ira Weiny
2023-02-06 22:16 ` Dave Jiang
2023-02-09 0:25 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 05/18] cxl/region: Add volatile region creation support Dan Williams
2023-02-06 16:18 ` Jonathan Cameron
2023-02-06 18:19 ` Dan Williams
2023-02-06 16:55 ` Gregory Price
2023-02-06 21:57 ` Dan Williams
2023-02-06 19:56 ` Gregory Price
2023-02-06 19:25 ` Ira Weiny
2023-02-06 22:31 ` Dave Jiang
2023-02-06 22:37 ` Dan Williams
2023-02-09 1:02 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 06/18] cxl/region: Refactor attach_target() for autodiscovery Dan Williams
2023-02-06 17:06 ` Jonathan Cameron
2023-02-06 18:48 ` Dan Williams
2023-02-06 19:26 ` Ira Weiny
2023-02-06 22:41 ` Dave Jiang
2023-02-09 1:09 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 07/18] cxl/region: Move region-position validation to a helper Dan Williams
2023-02-06 17:44 ` Ira Weiny
2023-02-06 19:15 ` Dan Williams
2023-02-08 12:30 ` Jonathan Cameron
2023-02-09 4:09 ` Dan Williams
2023-02-09 4:26 ` Dan Williams
2023-02-09 11:07 ` Jonathan Cameron
2023-02-09 20:52 ` Dan Williams
2023-02-09 19:45 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 08/18] kernel/range: Uplevel the cxl subsystem's range_contains() helper Dan Williams
2023-02-06 17:02 ` Gregory Price
2023-02-06 22:01 ` Dan Williams
2023-02-06 19:28 ` Ira Weiny
2023-02-06 23:41 ` Dave Jiang
2023-02-08 12:32 ` Jonathan Cameron
2023-02-09 19:47 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 09/18] cxl/region: Enable CONFIG_CXL_REGION to be toggled Dan Williams
2023-02-06 17:03 ` Gregory Price
2023-02-06 23:57 ` Dave Jiang
2023-02-08 12:36 ` Jonathan Cameron
2023-02-09 20:17 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 10/18] cxl/region: Fix passthrough-decoder detection Dan Williams
2023-02-06 5:38 ` Greg KH
2023-02-06 17:22 ` Dan Williams
2023-02-07 0:00 ` Dave Jiang
2023-02-08 12:44 ` Jonathan Cameron
2023-02-09 20:28 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 11/18] cxl/region: Add region autodiscovery Dan Williams
2023-02-06 19:02 ` Ira Weiny
2023-02-07 23:54 ` Dave Jiang
2023-02-08 17:07 ` Jonathan Cameron
2023-02-09 4:07 ` Dan Williams
2023-02-06 1:03 ` [PATCH 12/18] tools/testing/cxl: Define a fixed volatile configuration to parse Dan Williams
2023-02-08 17:31 ` Jonathan Cameron
2023-02-09 20:50 ` Dan Williams [this message]
2023-02-06 1:03 ` [PATCH 13/18] dax/hmem: Move HMAT and Soft reservation probe initcall level Dan Williams
2023-02-06 1:03 ` [PATCH 14/18] dax/hmem: Drop unnecessary dax_hmem_remove() Dan Williams
2023-02-06 17:15 ` Gregory Price
2023-02-08 17:33 ` Jonathan Cameron
2023-02-06 1:03 ` [PATCH 15/18] dax/hmem: Convey the dax range via memregion_info() Dan Williams
2023-02-08 17:35 ` Jonathan Cameron
2023-02-06 1:03 ` [PATCH 16/18] dax/hmem: Move hmem device registration to dax_hmem.ko Dan Williams
2023-02-06 1:04 ` [PATCH 17/18] dax: Assign RAM regions to memory-hotplug by default Dan Williams
2023-02-06 17:26 ` Gregory Price
2023-02-06 22:15 ` Dan Williams
2023-02-06 19:05 ` Gregory Price
2023-02-06 23:20 ` Dan Williams
2023-02-06 1:04 ` [PATCH 18/18] cxl/dax: Create dax devices for CXL RAM regions Dan Williams
2023-02-06 5:36 ` [PATCH 00/18] CXL RAM and the 'Soft Reserved' => 'System RAM' default Gregory Price
2023-02-06 16:40 ` Davidlohr Bueso
2023-02-06 18:23 ` Dan Williams
2023-02-06 17:29 ` Dan Williams
2023-02-06 17:18 ` Davidlohr Bueso
[not found] ` <CGME20230208173730uscas1p2af3a9eeb8946dfa607b190c079a49653@uscas1p2.samsung.com>
2023-02-08 17:37 ` Fan Ni
2023-02-09 4:56 ` Dan Williams
2023-02-13 12:13 ` David Hildenbrand
2023-02-14 18:45 ` Dan Williams
2023-02-14 18:27 ` Gregory Price
2023-02-14 18:39 ` Dan Williams
2023-02-14 19:01 ` Gregory Price
2023-02-14 21:18 ` Jonathan Cameron
2023-02-14 21:51 ` Gregory Price
2023-02-14 21:54 ` Gregory Price
2023-02-15 10:03 ` Jonathan Cameron
2023-02-18 9:47 ` Gregory Price
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